fsl_iim.c 6.2 KB

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  1. /*
  2. * (C) Copyright 2009-2013 ADVANSEE
  3. * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
  4. *
  5. * Based on the mpc512x iim code:
  6. * Copyright 2008 Silicon Turnkey Express, Inc.
  7. * Martha Marx <mmarx@silicontkx.com>
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <common.h>
  28. #include <fuse.h>
  29. #include <asm/errno.h>
  30. #include <asm/io.h>
  31. #ifndef CONFIG_MPC512X
  32. #include <asm/arch/imx-regs.h>
  33. #endif
  34. /* FSL IIM-specific constants */
  35. #define STAT_BUSY 0x80
  36. #define STAT_PRGD 0x02
  37. #define STAT_SNSD 0x01
  38. #define STATM_PRGD_M 0x02
  39. #define STATM_SNSD_M 0x01
  40. #define ERR_PRGE 0x80
  41. #define ERR_WPE 0x40
  42. #define ERR_OPE 0x20
  43. #define ERR_RPE 0x10
  44. #define ERR_WLRE 0x08
  45. #define ERR_SNSE 0x04
  46. #define ERR_PARITYE 0x02
  47. #define EMASK_PRGE_M 0x80
  48. #define EMASK_WPE_M 0x40
  49. #define EMASK_OPE_M 0x20
  50. #define EMASK_RPE_M 0x10
  51. #define EMASK_WLRE_M 0x08
  52. #define EMASK_SNSE_M 0x04
  53. #define EMASK_PARITYE_M 0x02
  54. #define FCTL_DPC 0x80
  55. #define FCTL_PRG_LENGTH_MASK 0x70
  56. #define FCTL_ESNS_N 0x08
  57. #define FCTL_ESNS_0 0x04
  58. #define FCTL_ESNS_1 0x02
  59. #define FCTL_PRG 0x01
  60. #define UA_A_BANK_MASK 0x38
  61. #define UA_A_ROWH_MASK 0x07
  62. #define LA_A_ROWL_MASK 0xf8
  63. #define LA_A_BIT_MASK 0x07
  64. #define PREV_PROD_REV_MASK 0xf8
  65. #define PREV_PROD_VT_MASK 0x07
  66. /* Select the correct accessors depending on endianness */
  67. #if __BYTE_ORDER == __LITTLE_ENDIAN
  68. #define iim_read32 in_le32
  69. #define iim_write32 out_le32
  70. #define iim_clrsetbits32 clrsetbits_le32
  71. #define iim_clrbits32 clrbits_le32
  72. #define iim_setbits32 setbits_le32
  73. #elif __BYTE_ORDER == __BIG_ENDIAN
  74. #define iim_read32 in_be32
  75. #define iim_write32 out_be32
  76. #define iim_clrsetbits32 clrsetbits_be32
  77. #define iim_clrbits32 clrbits_be32
  78. #define iim_setbits32 setbits_be32
  79. #else
  80. #error Endianess is not defined: please fix to continue
  81. #endif
  82. /* IIM control registers */
  83. struct fsl_iim {
  84. u32 stat;
  85. u32 statm;
  86. u32 err;
  87. u32 emask;
  88. u32 fctl;
  89. u32 ua;
  90. u32 la;
  91. u32 sdat;
  92. u32 prev;
  93. u32 srev;
  94. u32 prg_p;
  95. u32 scs[0x1f5];
  96. struct {
  97. u32 word[0x100];
  98. } bank[8];
  99. };
  100. static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
  101. const char *caller)
  102. {
  103. *regs = (struct fsl_iim *)IIM_BASE_ADDR;
  104. if (bank >= ARRAY_SIZE((*regs)->bank) ||
  105. word >= ARRAY_SIZE((*regs)->bank[0].word) ||
  106. !assert) {
  107. printf("fsl_iim %s(): Invalid argument\n", caller);
  108. return -EINVAL;
  109. }
  110. return 0;
  111. }
  112. static void clear_status(struct fsl_iim *regs)
  113. {
  114. iim_setbits32(&regs->stat, 0);
  115. iim_setbits32(&regs->err, 0);
  116. }
  117. static void finish_access(struct fsl_iim *regs, u32 *stat, u32 *err)
  118. {
  119. *stat = iim_read32(&regs->stat);
  120. *err = iim_read32(&regs->err);
  121. clear_status(regs);
  122. }
  123. static int prepare_read(struct fsl_iim **regs, u32 bank, u32 word, u32 *val,
  124. const char *caller)
  125. {
  126. int ret;
  127. ret = prepare_access(regs, bank, word, val != NULL, caller);
  128. if (ret)
  129. return ret;
  130. clear_status(*regs);
  131. return 0;
  132. }
  133. int fuse_read(u32 bank, u32 word, u32 *val)
  134. {
  135. struct fsl_iim *regs;
  136. u32 stat, err;
  137. int ret;
  138. ret = prepare_read(&regs, bank, word, val, __func__);
  139. if (ret)
  140. return ret;
  141. *val = iim_read32(&regs->bank[bank].word[word]);
  142. finish_access(regs, &stat, &err);
  143. if (err & ERR_RPE) {
  144. puts("fsl_iim fuse_read(): Read protect error\n");
  145. return -EIO;
  146. }
  147. return 0;
  148. }
  149. static void direct_access(struct fsl_iim *regs, u32 bank, u32 word, u32 bit,
  150. u32 fctl, u32 *stat, u32 *err)
  151. {
  152. iim_write32(&regs->ua, bank << 3 | word >> 5);
  153. iim_write32(&regs->la, (word << 3 | bit) & 0xff);
  154. if (fctl == FCTL_PRG)
  155. iim_write32(&regs->prg_p, 0xaa);
  156. iim_setbits32(&regs->fctl, fctl);
  157. while (iim_read32(&regs->stat) & STAT_BUSY)
  158. udelay(20);
  159. finish_access(regs, stat, err);
  160. }
  161. int fuse_sense(u32 bank, u32 word, u32 *val)
  162. {
  163. struct fsl_iim *regs;
  164. u32 stat, err;
  165. int ret;
  166. ret = prepare_read(&regs, bank, word, val, __func__);
  167. if (ret)
  168. return ret;
  169. direct_access(regs, bank, word, 0, FCTL_ESNS_N, &stat, &err);
  170. if (err & ERR_SNSE) {
  171. puts("fsl_iim fuse_sense(): Explicit sense cycle error\n");
  172. return -EIO;
  173. }
  174. if (!(stat & STAT_SNSD)) {
  175. puts("fsl_iim fuse_sense(): Explicit sense cycle did not complete\n");
  176. return -EIO;
  177. }
  178. *val = iim_read32(&regs->sdat);
  179. return 0;
  180. }
  181. static int prog_bit(struct fsl_iim *regs, u32 bank, u32 word, u32 bit)
  182. {
  183. u32 stat, err;
  184. clear_status(regs);
  185. direct_access(regs, bank, word, bit, FCTL_PRG, &stat, &err);
  186. iim_write32(&regs->prg_p, 0x00);
  187. if (err & ERR_PRGE) {
  188. puts("fsl_iim fuse_prog(): Program error\n");
  189. return -EIO;
  190. }
  191. if (err & ERR_WPE) {
  192. puts("fsl_iim fuse_prog(): Write protect error\n");
  193. return -EIO;
  194. }
  195. if (!(stat & STAT_PRGD)) {
  196. puts("fsl_iim fuse_prog(): Program did not complete\n");
  197. return -EIO;
  198. }
  199. return 0;
  200. }
  201. static int prepare_write(struct fsl_iim **regs, u32 bank, u32 word, u32 val,
  202. const char *caller)
  203. {
  204. return prepare_access(regs, bank, word, !(val & ~0xff), caller);
  205. }
  206. int fuse_prog(u32 bank, u32 word, u32 val)
  207. {
  208. struct fsl_iim *regs;
  209. u32 bit;
  210. int ret;
  211. ret = prepare_write(&regs, bank, word, val, __func__);
  212. if (ret)
  213. return ret;
  214. for (bit = 0; val; bit++, val >>= 1)
  215. if (val & 0x01) {
  216. ret = prog_bit(regs, bank, word, bit);
  217. if (ret)
  218. return ret;
  219. }
  220. return 0;
  221. }
  222. int fuse_override(u32 bank, u32 word, u32 val)
  223. {
  224. struct fsl_iim *regs;
  225. u32 stat, err;
  226. int ret;
  227. ret = prepare_write(&regs, bank, word, val, __func__);
  228. if (ret)
  229. return ret;
  230. clear_status(regs);
  231. iim_write32(&regs->bank[bank].word[word], val);
  232. finish_access(regs, &stat, &err);
  233. if (err & ERR_OPE) {
  234. puts("fsl_iim fuse_override(): Override protect error\n");
  235. return -EIO;
  236. }
  237. return 0;
  238. }