imx-regs.h 10 KB

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  1. /*
  2. * Copyright (C) 2009, DENX Software Engineering
  3. * Author: John Rigby <jcrigby@gmail.com
  4. *
  5. * Based on arch-mx31/imx-regs.h
  6. * Copyright (C) 2009 Ilya Yanok,
  7. * Emcraft Systems <yanok@emcraft.com>
  8. * and arch-mx27/imx-regs.h
  9. * Copyright (C) 2007 Pengutronix,
  10. * Sascha Hauer <s.hauer@pengutronix.de>
  11. * Copyright (C) 2009 Ilya Yanok,
  12. * Emcraft Systems <yanok@emcraft.com>
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. */
  32. #ifndef _IMX_REGS_H
  33. #define _IMX_REGS_H
  34. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  35. #include <asm/types.h>
  36. /* Clock Control Module (CCM) registers */
  37. struct ccm_regs {
  38. u32 mpctl; /* Core PLL Control */
  39. u32 upctl; /* USB PLL Control */
  40. u32 cctl; /* Clock Control */
  41. u32 cgr0; /* Clock Gating Control 0 */
  42. u32 cgr1; /* Clock Gating Control 1 */
  43. u32 cgr2; /* Clock Gating Control 2 */
  44. u32 pcdr[4]; /* PER Clock Dividers */
  45. u32 rcsr; /* CCM Status */
  46. u32 crdr; /* CCM Reset and Debug */
  47. u32 dcvr0; /* DPTC Comparator Value 0 */
  48. u32 dcvr1; /* DPTC Comparator Value 1 */
  49. u32 dcvr2; /* DPTC Comparator Value 2 */
  50. u32 dcvr3; /* DPTC Comparator Value 3 */
  51. u32 ltr0; /* Load Tracking 0 */
  52. u32 ltr1; /* Load Tracking 1 */
  53. u32 ltr2; /* Load Tracking 2 */
  54. u32 ltr3; /* Load Tracking 3 */
  55. u32 ltbr0; /* Load Tracking Buffer 0 */
  56. u32 ltbr1; /* Load Tracking Buffer 1 */
  57. u32 pcmr0; /* Power Management Control 0 */
  58. u32 pcmr1; /* Power Management Control 1 */
  59. u32 pcmr2; /* Power Management Control 2 */
  60. u32 mcr; /* Miscellaneous Control */
  61. u32 lpimr0; /* Low Power Interrupt Mask 0 */
  62. u32 lpimr1; /* Low Power Interrupt Mask 1 */
  63. };
  64. /* Enhanced SDRAM Controller (ESDRAMC) registers */
  65. struct esdramc_regs {
  66. u32 ctl0; /* control 0 */
  67. u32 cfg0; /* configuration 0 */
  68. u32 ctl1; /* control 1 */
  69. u32 cfg1; /* configuration 1 */
  70. u32 misc; /* miscellaneous */
  71. u32 pad[3];
  72. u32 cdly1; /* Delay Line 1 configuration debug */
  73. u32 cdly2; /* delay line 2 configuration debug */
  74. u32 cdly3; /* delay line 3 configuration debug */
  75. u32 cdly4; /* delay line 4 configuration debug */
  76. u32 cdly5; /* delay line 5 configuration debug */
  77. u32 cdlyl; /* delay line cycle length debug */
  78. };
  79. /* General Purpose Timer (GPT) registers */
  80. struct gpt_regs {
  81. u32 ctrl; /* control */
  82. u32 pre; /* prescaler */
  83. u32 stat; /* status */
  84. u32 intr; /* interrupt */
  85. u32 cmp[3]; /* output compare 1-3 */
  86. u32 capt[2]; /* input capture 1-2 */
  87. u32 counter; /* counter */
  88. };
  89. /* Watchdog Timer (WDOG) registers */
  90. struct wdog_regs {
  91. u16 wcr; /* Control */
  92. u16 wsr; /* Service */
  93. u16 wrsr; /* Reset Status */
  94. u16 wicr; /* Interrupt Control */
  95. u16 wmcr; /* Misc Control */
  96. };
  97. /* IIM control registers */
  98. struct iim_regs {
  99. u32 iim_stat;
  100. u32 iim_statm;
  101. u32 iim_err;
  102. u32 iim_emask;
  103. u32 iim_fctl;
  104. u32 iim_ua;
  105. u32 iim_la;
  106. u32 iim_sdat;
  107. u32 iim_prev;
  108. u32 iim_srev;
  109. u32 iim_prg_p;
  110. u32 iim_scs0;
  111. u32 iim_scs1;
  112. u32 iim_scs2;
  113. u32 iim_scs3;
  114. u32 res1[0x1f1];
  115. struct fuse_bank {
  116. u32 fuse_regs[0x20];
  117. u32 fuse_rsvd[0xe0];
  118. } bank[3];
  119. };
  120. struct fuse_bank0_regs {
  121. u32 fuse0_7[8];
  122. u32 uid[8];
  123. u32 fuse16_25[0xa];
  124. u32 mac_addr[6];
  125. };
  126. struct fuse_bank1_regs {
  127. u32 fuse0_21[0x16];
  128. u32 usr5;
  129. u32 fuse23_29[7];
  130. u32 usr6[2];
  131. };
  132. /* Multi-Layer AHB Crossbar Switch (MAX) registers */
  133. struct max_regs {
  134. u32 mpr0;
  135. u32 pad00[3];
  136. u32 sgpcr0;
  137. u32 pad01[59];
  138. u32 mpr1;
  139. u32 pad02[3];
  140. u32 sgpcr1;
  141. u32 pad03[59];
  142. u32 mpr2;
  143. u32 pad04[3];
  144. u32 sgpcr2;
  145. u32 pad05[59];
  146. u32 mpr3;
  147. u32 pad06[3];
  148. u32 sgpcr3;
  149. u32 pad07[59];
  150. u32 mpr4;
  151. u32 pad08[3];
  152. u32 sgpcr4;
  153. u32 pad09[251];
  154. u32 mgpcr0;
  155. u32 pad10[63];
  156. u32 mgpcr1;
  157. u32 pad11[63];
  158. u32 mgpcr2;
  159. u32 pad12[63];
  160. u32 mgpcr3;
  161. u32 pad13[63];
  162. u32 mgpcr4;
  163. };
  164. /* AHB <-> IP-Bus Interface (AIPS) */
  165. struct aips_regs {
  166. u32 mpr_0_7;
  167. u32 mpr_8_15;
  168. };
  169. #endif
  170. #define ARCH_MXC
  171. /* AIPS 1 */
  172. #define IMX_AIPS1_BASE (0x43F00000)
  173. #define IMX_MAX_BASE (0x43F04000)
  174. #define IMX_CLKCTL_BASE (0x43F08000)
  175. #define IMX_ETB_SLOT4_BASE (0x43F0C000)
  176. #define IMX_ETB_SLOT5_BASE (0x43F10000)
  177. #define IMX_ECT_CTIO_BASE (0x43F18000)
  178. #define IMX_I2C_BASE (0x43F80000)
  179. #define IMX_I2C3_BASE (0x43F84000)
  180. #define IMX_CAN1_BASE (0x43F88000)
  181. #define IMX_CAN2_BASE (0x43F8C000)
  182. #define UART1_BASE (0x43F90000)
  183. #define UART2_BASE (0x43F94000)
  184. #define IMX_I2C2_BASE (0x43F98000)
  185. #define IMX_OWIRE_BASE (0x43F9C000)
  186. #define IMX_CSPI1_BASE (0x43FA4000)
  187. #define IMX_KPP_BASE (0x43FA8000)
  188. #define IMX_IOPADMUX_BASE (0x43FAC000)
  189. #define IMX_IOPADCTL_BASE (0x43FAC22C)
  190. #define IMX_IOPADGRPCTL_BASE (0x43FAC418)
  191. #define IMX_IOPADINPUTSEL_BASE (0x43FAC460)
  192. #define IMX_AUDMUX_BASE (0x43FB0000)
  193. #define IMX_ECT_IP1_BASE (0x43FB8000)
  194. #define IMX_ECT_IP2_BASE (0x43FBC000)
  195. /* SPBA */
  196. #define IMX_SPBA_BASE (0x50000000)
  197. #define IMX_CSPI3_BASE (0x50004000)
  198. #define UART4_BASE (0x50008000)
  199. #define UART3_BASE (0x5000C000)
  200. #define IMX_CSPI2_BASE (0x50010000)
  201. #define IMX_SSI2_BASE (0x50014000)
  202. #define IMX_ESAI_BASE (0x50018000)
  203. #define IMX_ATA_DMA_BASE (0x50020000)
  204. #define IMX_SIM1_BASE (0x50024000)
  205. #define IMX_SIM2_BASE (0x50028000)
  206. #define UART5_BASE (0x5002C000)
  207. #define IMX_TSC_BASE (0x50030000)
  208. #define IMX_SSI1_BASE (0x50034000)
  209. #define IMX_FEC_BASE (0x50038000)
  210. #define IMX_SPBA_CTRL_BASE (0x5003C000)
  211. /* AIPS 2 */
  212. #define IMX_AIPS2_BASE (0x53F00000)
  213. #define IMX_CCM_BASE (0x53F80000)
  214. #define IMX_GPT4_BASE (0x53F84000)
  215. #define IMX_GPT3_BASE (0x53F88000)
  216. #define IMX_GPT2_BASE (0x53F8C000)
  217. #define IMX_GPT1_BASE (0x53F90000)
  218. #define IMX_EPIT1_BASE (0x53F94000)
  219. #define IMX_EPIT2_BASE (0x53F98000)
  220. #define IMX_GPIO4_BASE (0x53F9C000)
  221. #define IMX_PWM2_BASE (0x53FA0000)
  222. #define IMX_GPIO3_BASE (0x53FA4000)
  223. #define IMX_PWM3_BASE (0x53FA8000)
  224. #define IMX_SCC_BASE (0x53FAC000)
  225. #define IMX_SCM_BASE (0x53FAE000)
  226. #define IMX_SMN_BASE (0x53FAF000)
  227. #define IMX_RNGD_BASE (0x53FB0000)
  228. #define IMX_MMC_SDHC1_BASE (0x53FB4000)
  229. #define IMX_MMC_SDHC2_BASE (0x53FB8000)
  230. #define IMX_LCDC_BASE (0x53FBC000)
  231. #define IMX_SLCDC_BASE (0x53FC0000)
  232. #define IMX_PWM4_BASE (0x53FC8000)
  233. #define IMX_GPIO1_BASE (0x53FCC000)
  234. #define IMX_GPIO2_BASE (0x53FD0000)
  235. #define IMX_SDMA_BASE (0x53FD4000)
  236. #define IMX_WDT_BASE (0x53FDC000)
  237. #define IMX_PWM1_BASE (0x53FE0000)
  238. #define IMX_RTIC_BASE (0x53FEC000)
  239. #define IMX_IIM_BASE (0x53FF0000)
  240. #define IIM_BASE_ADDR IMX_IIM_BASE
  241. #define IMX_USB_BASE (0x53FF4000)
  242. #define IMX_USB_PORT_OFFSET 0x200
  243. #define IMX_CSI_BASE (0x53FF8000)
  244. #define IMX_DRYICE_BASE (0x53FFC000)
  245. #define IMX_ARM926_ROMPATCH (0x60000000)
  246. #define IMX_ARM926_ASIC (0x68000000)
  247. /* 128K Internal Static RAM */
  248. #define IMX_RAM_BASE (0x78000000)
  249. #define IMX_RAM_SIZE (128 * 1024)
  250. /* SDRAM BANKS */
  251. #define IMX_SDRAM_BANK0_BASE (0x80000000)
  252. #define IMX_SDRAM_BANK1_BASE (0x90000000)
  253. #define IMX_WEIM_CS0 (0xA0000000)
  254. #define IMX_WEIM_CS1 (0xA8000000)
  255. #define IMX_WEIM_CS2 (0xB0000000)
  256. #define IMX_WEIM_CS3 (0xB2000000)
  257. #define IMX_WEIM_CS4 (0xB4000000)
  258. #define IMX_ESDRAMC_BASE (0xB8001000)
  259. #define IMX_WEIM_CTRL_BASE (0xB8002000)
  260. #define IMX_M3IF_CTRL_BASE (0xB8003000)
  261. #define IMX_EMI_CTRL_BASE (0xB8004000)
  262. /* NAND Flash Controller */
  263. #define IMX_NFC_BASE (0xBB000000)
  264. #define NFC_BASE_ADDR IMX_NFC_BASE
  265. /* CCM bitfields */
  266. #define CCM_PLL_MFI_SHIFT 10
  267. #define CCM_PLL_MFI_MASK 0xf
  268. #define CCM_PLL_MFN_SHIFT 0
  269. #define CCM_PLL_MFN_MASK 0x3ff
  270. #define CCM_PLL_MFD_SHIFT 16
  271. #define CCM_PLL_MFD_MASK 0x3ff
  272. #define CCM_PLL_PD_SHIFT 26
  273. #define CCM_PLL_PD_MASK 0xf
  274. #define CCM_CCTL_ARM_DIV_SHIFT 30
  275. #define CCM_CCTL_ARM_DIV_MASK 3
  276. #define CCM_CCTL_AHB_DIV_SHIFT 28
  277. #define CCM_CCTL_AHB_DIV_MASK 3
  278. #define CCM_CCTL_ARM_SRC (1 << 14)
  279. #define CCM_CGR1_GPT1 (1 << 19)
  280. #define CCM_PERCLK_REG(clk) (clk / 4)
  281. #define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4))
  282. #define CCM_PERCLK_MASK 0x3f
  283. #define CCM_RCSR_NF_16BIT_SEL (1 << 14)
  284. #define CCM_RCSR_NF_PS(v) ((v >> 26) & 3)
  285. /* ESDRAM Controller register bitfields */
  286. #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
  287. #define ESDCTL_BL (1 << 7)
  288. #define ESDCTL_FP (1 << 8)
  289. #define ESDCTL_PWDT(x) (((x) & 3) << 10)
  290. #define ESDCTL_SREFR(x) (((x) & 7) << 13)
  291. #define ESDCTL_DSIZ_16_UPPER (0 << 16)
  292. #define ESDCTL_DSIZ_16_LOWER (1 << 16)
  293. #define ESDCTL_DSIZ_32 (2 << 16)
  294. #define ESDCTL_COL8 (0 << 20)
  295. #define ESDCTL_COL9 (1 << 20)
  296. #define ESDCTL_COL10 (2 << 20)
  297. #define ESDCTL_ROW11 (0 << 24)
  298. #define ESDCTL_ROW12 (1 << 24)
  299. #define ESDCTL_ROW13 (2 << 24)
  300. #define ESDCTL_ROW14 (3 << 24)
  301. #define ESDCTL_ROW15 (4 << 24)
  302. #define ESDCTL_SP (1 << 27)
  303. #define ESDCTL_SMODE_NORMAL (0 << 28)
  304. #define ESDCTL_SMODE_PRECHARGE (1 << 28)
  305. #define ESDCTL_SMODE_AUTO_REF (2 << 28)
  306. #define ESDCTL_SMODE_LOAD_MODE (3 << 28)
  307. #define ESDCTL_SMODE_MAN_REF (4 << 28)
  308. #define ESDCTL_SDE (1 << 31)
  309. #define ESDCFG_TRC(x) (((x) & 0xf) << 0)
  310. #define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
  311. #define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
  312. #define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
  313. #define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
  314. #define ESDCFG_TWR (1 << 15)
  315. #define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
  316. #define ESDCFG_TRP(x) (((x) & 0x3) << 18)
  317. #define ESDCFG_TWTR (1 << 20)
  318. #define ESDCFG_TXP(x) (((x) & 0x3) << 21)
  319. #define ESDMISC_RST (1 << 1)
  320. #define ESDMISC_MDDREN (1 << 2)
  321. #define ESDMISC_MDDR_DL_RST (1 << 3)
  322. #define ESDMISC_MDDR_MDIS (1 << 4)
  323. #define ESDMISC_LHD (1 << 5)
  324. #define ESDMISC_MA10_SHARE (1 << 6)
  325. #define ESDMISC_SDRAM_RDY (1 << 31)
  326. /* GPT bits */
  327. #define GPT_CTRL_SWR (1 << 15) /* Software reset */
  328. #define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */
  329. #define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */
  330. #define GPT_CTRL_TEN 1 /* Timer enable */
  331. /* WDOG enable */
  332. #define WCR_WDE 0x04
  333. #define WSR_UNLOCK1 0x5555
  334. #define WSR_UNLOCK2 0xAAAA
  335. /* Names used in GPIO driver */
  336. #define GPIO1_BASE_ADDR IMX_GPIO1_BASE
  337. #define GPIO2_BASE_ADDR IMX_GPIO2_BASE
  338. #define GPIO3_BASE_ADDR IMX_GPIO3_BASE
  339. #define GPIO4_BASE_ADDR IMX_GPIO4_BASE
  340. #define CHIP_REV_1_0 0x10
  341. #define CHIP_REV_1_1 0x11
  342. #define CHIP_REV_1_2 0x12
  343. #endif /* _IMX_REGS_H */