README.P1010RDB-PA 6.6 KB

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  1. Overview
  2. =========
  3. The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
  4. The P1010 is a cost-effective, low-power, highly integrated host processor
  5. based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
  6. that addresses the requirements of several routing, gateways, storage, consumer,
  7. and industrial applications. Applications of interest include the main CPUs and
  8. I/O processors in network attached storage (NAS), the voice over IP (VoIP)
  9. router/gateway, and wireless LAN (WLAN) and industrial controllers.
  10. The P1010RDB board features are as follows:
  11. Memory subsystem:
  12. - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
  13. - 32 Mbyte NOR flash single-chip memory
  14. - 32 Mbyte NAND flash memory
  15. - 256 Kbit M24256 I2C EEPROM
  16. - 16 Mbyte SPI memory
  17. - I2C Board EEPROM 128x8 bit memory
  18. - SD/MMC connector to interface with the SD memory card
  19. Interfaces:
  20. - PCIe:
  21. - Lane0: x1 mini-PCIe slot
  22. - Lane1: x1 PCIe standard slot
  23. - SATA:
  24. - 1 internal SATA connector to 2.5” 160G SATA2 HDD
  25. - 1 eSATA connector to rear panel
  26. - 10/100/1000 BaseT Ethernet ports:
  27. - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
  28. - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
  29. - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
  30. - USB 2.0 port:
  31. - x1 USB2.0 port via an external ULPI PHY to micro-AB connector
  32. - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
  33. - FlexCAN ports:
  34. - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
  35. interface;
  36. - DUART interface:
  37. - DUART interface: supports two UARTs up to 115200 bps for
  38. console display
  39. - RJ45 connectors are used for these 2 UART ports.
  40. - TDM
  41. - 2 FXS ports connected via an external SLIC to the TDM interface.
  42. SLIC is controllled via SPI.
  43. - 1 FXO port connected via a relay to FXS for switchover to POTS
  44. Board connectors:
  45. - Mini-ITX power supply connector
  46. - JTAG/COP for debugging
  47. IEEE Std. 1588 signals for test and measurement
  48. Real-time clock on I2C bus
  49. POR
  50. - support critical POR setting changed via switch on board
  51. PCB
  52. - 6-layer routing (4-layer signals, 2-layer power and ground)
  53. Physical Memory Map on P1010RDB
  54. ===============================
  55. Address Start Address End Memory type Attributes
  56. 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
  57. 0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
  58. 0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
  59. 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
  60. 0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
  61. 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
  62. 0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
  63. 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  64. Serial Port Configuration on P1010RDB
  65. =====================================
  66. Configure the serial port of the attached computer with the following values:
  67. -Data rate: 115200 bps
  68. -Number of data bits: 8
  69. -Parity: None
  70. -Number of Stop bits: 1
  71. -Flow Control: Hardware/None
  72. Settings of DIP-switch
  73. ======================
  74. SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
  75. SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
  76. SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
  77. Note: 1 stands for 'on', 0 stands for 'off'
  78. Setting of hwconfig
  79. ===================
  80. If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
  81. "fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
  82. setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
  83. By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
  84. is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
  85. instead of to CAN/UART1.
  86. Build and burn U-Boot to NOR flash
  87. ==================================
  88. 1. Build u-boot.bin image
  89. export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
  90. make P1010RDB_NOR
  91. 2. Burn u-boot.bin into NOR flash
  92. => tftp $loadaddr $uboot
  93. => protect off eff40000 +$filesize
  94. => erase eff40000 +$filesize
  95. => cp.b $loadaddr eff40000 $filesize
  96. 3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
  97. Alternate NOR bank
  98. ==================
  99. 1. Burn u-boot.bin into alternate NOR bank
  100. => tftp $loadaddr $uboot
  101. => protect off eef40000 +$filesize
  102. => erase eef40000 +$filesize
  103. => cp.b $loadaddr eef40000 $filesize
  104. 2. Switch to alternate NOR bank
  105. => mw.b ffb00009 1
  106. => reset
  107. or set SW1[8]= ON
  108. SW1[8]= OFF: Upper bank used for booting start
  109. SW1[8]= ON: Lower bank used for booting start
  110. CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
  111. 0 - boot from upper 4 sectors
  112. 1 - boot from lower 4 sectors
  113. Build and burn U-Boot to NAND flash
  114. ===================================
  115. 1. Build u-boot.bin image
  116. export ARCH=powerpc
  117. export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
  118. make P1010RDB_NAND
  119. 2. Burn u-boot-nand.bin into NAND flash
  120. => tftp $loadaddr $uboot-nand
  121. => nand erase 0 $filesize
  122. => nand write $loadaddr 0 $filesize
  123. 3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
  124. Build and burn U-Boot to SPI flash
  125. ==================================
  126. 1. Build u-boot-spi.bin image
  127. make P1010RDB_SPIFLASH_config; make
  128. Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
  129. Download u-boot.bin to linux and you can find some config files
  130. under /usr/share such as config_xx.dat. Do below command:
  131. boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
  132. u-boot-spi.bin
  133. to generate u-boot-spi.bin.
  134. 2. Burn u-boot-spi.bin into SPI flash
  135. => tftp $loadaddr $uboot-spi
  136. => sf erase 0 100000
  137. => sf write $loadaddr 0 $filesize
  138. 3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
  139. CPLD POR setting registers
  140. ==========================
  141. 1. Set POR switch selection register (addr 0xFFB00011) to 0.
  142. 2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
  143. proper values.
  144. If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
  145. switch command by I2C.
  146. 3. Send reset command.
  147. After reset, the new POR setting will be implemented.
  148. Two examples are given in below:
  149. Switch from NOR to NAND boot with default frequency:
  150. => i2c dev 0
  151. => i2c mw 18 1 f9
  152. => i2c mw 18 3 f0
  153. => mw.b ffb00011 0
  154. => mw.b ffb00017 1
  155. => reset
  156. Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
  157. => i2c dev 0
  158. => i2c mw 18 1 f1
  159. => i2c mw 18 3 f0
  160. => mw.b ffb00011 0
  161. => mw.b ffb00014 2
  162. => mw.b ffb00015 5
  163. => mw.b ffb00016 3
  164. => mw.b ffb00017 f
  165. => reset
  166. Boot Linux from network using TFTP on P1010RDB
  167. ==============================================
  168. Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
  169. => tftp 1000000 uImage
  170. => tftp 2000000 p1010rdb.dtb
  171. => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
  172. => bootm 1000000 3000000 2000000
  173. For more details, please refer to P1010RDB User Guide and access website
  174. www.freescale.com