pinmux.h 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616
  1. /*
  2. * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. #ifndef _TEGRA114_PINMUX_H_
  17. #define _TEGRA114_PINMUX_H_
  18. /*
  19. * Pin groups which we adjust. There are three basic attributes of each pin
  20. * group which use this enum:
  21. *
  22. * - function
  23. * - pullup / pulldown
  24. * - tristate or normal
  25. */
  26. enum pmux_pingrp {
  27. PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
  28. PINGRP_ULPI_DATA1,
  29. PINGRP_ULPI_DATA2,
  30. PINGRP_ULPI_DATA3,
  31. PINGRP_ULPI_DATA4,
  32. PINGRP_ULPI_DATA5,
  33. PINGRP_ULPI_DATA6,
  34. PINGRP_ULPI_DATA7,
  35. PINGRP_ULPI_CLK,
  36. PINGRP_ULPI_DIR,
  37. PINGRP_ULPI_NXT,
  38. PINGRP_ULPI_STP,
  39. PINGRP_DAP3_FS,
  40. PINGRP_DAP3_DIN,
  41. PINGRP_DAP3_DOUT,
  42. PINGRP_DAP3_SCLK,
  43. PINGRP_GPIO_PV0,
  44. PINGRP_GPIO_PV1,
  45. PINGRP_SDMMC1_CLK,
  46. PINGRP_SDMMC1_CMD,
  47. PINGRP_SDMMC1_DAT3,
  48. PINGRP_SDMMC1_DAT2,
  49. PINGRP_SDMMC1_DAT1,
  50. PINGRP_SDMMC1_DAT0,
  51. PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
  52. PINGRP_CLK2_REQ,
  53. PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
  54. PINGRP_DDC_SCL,
  55. PINGRP_DDC_SDA,
  56. PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
  57. PINGRP_UART2_TXD,
  58. PINGRP_UART2_RTS_N,
  59. PINGRP_UART2_CTS_N,
  60. PINGRP_UART3_TXD,
  61. PINGRP_UART3_RXD,
  62. PINGRP_UART3_CTS_N,
  63. PINGRP_UART3_RTS_N,
  64. PINGRP_GPIO_PU0,
  65. PINGRP_GPIO_PU1,
  66. PINGRP_GPIO_PU2,
  67. PINGRP_GPIO_PU3,
  68. PINGRP_GPIO_PU4,
  69. PINGRP_GPIO_PU5,
  70. PINGRP_GPIO_PU6,
  71. PINGRP_GEN1_I2C_SDA,
  72. PINGRP_GEN1_I2C_SCL,
  73. PINGRP_DAP4_FS,
  74. PINGRP_DAP4_DIN,
  75. PINGRP_DAP4_DOUT,
  76. PINGRP_DAP4_SCLK,
  77. PINGRP_CLK3_OUT,
  78. PINGRP_CLK3_REQ,
  79. PINGRP_GMI_WP_N,
  80. PINGRP_GMI_IORDY,
  81. PINGRP_GMI_WAIT,
  82. PINGRP_GMI_ADV_N,
  83. PINGRP_GMI_CLK,
  84. PINGRP_GMI_CS0_N,
  85. PINGRP_GMI_CS1_N,
  86. PINGRP_GMI_CS2_N,
  87. PINGRP_GMI_CS3_N,
  88. PINGRP_GMI_CS4_N,
  89. PINGRP_GMI_CS6_N,
  90. PINGRP_GMI_CS7_N,
  91. PINGRP_GMI_AD0,
  92. PINGRP_GMI_AD1,
  93. PINGRP_GMI_AD2,
  94. PINGRP_GMI_AD3,
  95. PINGRP_GMI_AD4,
  96. PINGRP_GMI_AD5,
  97. PINGRP_GMI_AD6,
  98. PINGRP_GMI_AD7,
  99. PINGRP_GMI_AD8,
  100. PINGRP_GMI_AD9,
  101. PINGRP_GMI_AD10,
  102. PINGRP_GMI_AD11,
  103. PINGRP_GMI_AD12,
  104. PINGRP_GMI_AD13,
  105. PINGRP_GMI_AD14,
  106. PINGRP_GMI_AD15,
  107. PINGRP_GMI_A16,
  108. PINGRP_GMI_A17,
  109. PINGRP_GMI_A18,
  110. PINGRP_GMI_A19,
  111. PINGRP_GMI_WR_N,
  112. PINGRP_GMI_OE_N,
  113. PINGRP_GMI_DQS,
  114. PINGRP_GMI_RST_N,
  115. PINGRP_GEN2_I2C_SCL,
  116. PINGRP_GEN2_I2C_SDA,
  117. PINGRP_SDMMC4_CLK,
  118. PINGRP_SDMMC4_CMD,
  119. PINGRP_SDMMC4_DAT0,
  120. PINGRP_SDMMC4_DAT1,
  121. PINGRP_SDMMC4_DAT2,
  122. PINGRP_SDMMC4_DAT3,
  123. PINGRP_SDMMC4_DAT4,
  124. PINGRP_SDMMC4_DAT5,
  125. PINGRP_SDMMC4_DAT6,
  126. PINGRP_SDMMC4_DAT7,
  127. PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
  128. PINGRP_GPIO_PCC1,
  129. PINGRP_GPIO_PBB0,
  130. PINGRP_CAM_I2C_SCL,
  131. PINGRP_CAM_I2C_SDA,
  132. PINGRP_GPIO_PBB3,
  133. PINGRP_GPIO_PBB4,
  134. PINGRP_GPIO_PBB5,
  135. PINGRP_GPIO_PBB6,
  136. PINGRP_GPIO_PBB7,
  137. PINGRP_GPIO_PCC2,
  138. PINGRP_JTAG_RTCK,
  139. PINGRP_PWR_I2C_SCL,
  140. PINGRP_PWR_I2C_SDA,
  141. PINGRP_KB_ROW0,
  142. PINGRP_KB_ROW1,
  143. PINGRP_KB_ROW2,
  144. PINGRP_KB_ROW3,
  145. PINGRP_KB_ROW4,
  146. PINGRP_KB_ROW5,
  147. PINGRP_KB_ROW6,
  148. PINGRP_KB_ROW7,
  149. PINGRP_KB_ROW8,
  150. PINGRP_KB_ROW9,
  151. PINGRP_KB_ROW10,
  152. PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
  153. PINGRP_KB_COL1,
  154. PINGRP_KB_COL2,
  155. PINGRP_KB_COL3,
  156. PINGRP_KB_COL4,
  157. PINGRP_KB_COL5,
  158. PINGRP_KB_COL6,
  159. PINGRP_KB_COL7,
  160. PINGRP_CLK_32K_OUT,
  161. PINGRP_SYS_CLK_REQ,
  162. PINGRP_CORE_PWR_REQ,
  163. PINGRP_CPU_PWR_REQ,
  164. PINGRP_PWR_INT_N,
  165. PINGRP_CLK_32K_IN,
  166. PINGRP_OWR,
  167. PINGRP_DAP1_FS,
  168. PINGRP_DAP1_DIN,
  169. PINGRP_DAP1_DOUT,
  170. PINGRP_DAP1_SCLK,
  171. PINGRP_CLK1_REQ,
  172. PINGRP_CLK1_OUT,
  173. PINGRP_SPDIF_IN,
  174. PINGRP_SPDIF_OUT,
  175. PINGRP_DAP2_FS,
  176. PINGRP_DAP2_DIN,
  177. PINGRP_DAP2_DOUT,
  178. PINGRP_DAP2_SCLK,
  179. PINGRP_DVFS_PWM,
  180. PINGRP_GPIO_X1_AUD,
  181. PINGRP_GPIO_X3_AUD,
  182. PINGRP_DVFS_CLK,
  183. PINGRP_GPIO_X4_AUD,
  184. PINGRP_GPIO_X5_AUD,
  185. PINGRP_GPIO_X6_AUD,
  186. PINGRP_GPIO_X7_AUD,
  187. PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
  188. PINGRP_SDMMC3_CMD,
  189. PINGRP_SDMMC3_DAT0,
  190. PINGRP_SDMMC3_DAT1,
  191. PINGRP_SDMMC3_DAT2,
  192. PINGRP_SDMMC3_DAT3,
  193. PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
  194. PINGRP_SDMMC1_WP_N,
  195. PINGRP_SDMMC3_CD_N,
  196. PINGRP_GPIO_W2_AUD,
  197. PINGRP_GPIO_W3_AUD,
  198. PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
  199. PINGRP_USB_VBUS_EN1,
  200. PINGRP_SDMMC3_CLK_LB_IN,
  201. PINGRP_SDMMC3_CLK_LB_OUT,
  202. PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
  203. PINGRP_COUNT,
  204. };
  205. enum pdrive_pingrp {
  206. PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
  207. PDRIVE_PINGROUP_AO2,
  208. PDRIVE_PINGROUP_AT1,
  209. PDRIVE_PINGROUP_AT2,
  210. PDRIVE_PINGROUP_AT3,
  211. PDRIVE_PINGROUP_AT4,
  212. PDRIVE_PINGROUP_AT5,
  213. PDRIVE_PINGROUP_CDEV1,
  214. PDRIVE_PINGROUP_CDEV2,
  215. PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
  216. PDRIVE_PINGROUP_DAP2,
  217. PDRIVE_PINGROUP_DAP3,
  218. PDRIVE_PINGROUP_DAP4,
  219. PDRIVE_PINGROUP_DBG,
  220. PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
  221. PDRIVE_PINGROUP_SPI,
  222. PDRIVE_PINGROUP_UAA,
  223. PDRIVE_PINGROUP_UAB,
  224. PDRIVE_PINGROUP_UART2,
  225. PDRIVE_PINGROUP_UART3,
  226. PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
  227. PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
  228. PDRIVE_PINGROUP_GMA,
  229. PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
  230. PDRIVE_PINGROUP_GMF,
  231. PDRIVE_PINGROUP_GMG,
  232. PDRIVE_PINGROUP_GMH,
  233. PDRIVE_PINGROUP_OWR,
  234. PDRIVE_PINGROUP_UAD,
  235. PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
  236. PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
  237. PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
  238. PDRIVE_PINGROUP_DAP5,
  239. PDRIVE_PINGROUP_VBUS,
  240. PDRIVE_PINGROUP_AO3,
  241. PDRIVE_PINGROUP_HVC,
  242. PDRIVE_PINGROUP_SDIO4,
  243. PDRIVE_PINGROUP_AO0,
  244. PDRIVE_PINGROUP_COUNT,
  245. };
  246. /*
  247. * Functions which can be assigned to each of the pin groups. The values here
  248. * bear no relation to the values programmed into pinmux registers and are
  249. * purely a convenience. The translation is done through a table search.
  250. */
  251. enum pmux_func {
  252. PMUX_FUNC_AHB_CLK,
  253. PMUX_FUNC_APB_CLK,
  254. PMUX_FUNC_AUDIO_SYNC,
  255. PMUX_FUNC_CRT,
  256. PMUX_FUNC_DAP1,
  257. PMUX_FUNC_DAP2,
  258. PMUX_FUNC_DAP3,
  259. PMUX_FUNC_DAP4,
  260. PMUX_FUNC_DAP5,
  261. PMUX_FUNC_DISPA,
  262. PMUX_FUNC_DISPB,
  263. PMUX_FUNC_EMC_TEST0_DLL,
  264. PMUX_FUNC_EMC_TEST1_DLL,
  265. PMUX_FUNC_GMI,
  266. PMUX_FUNC_GMI_INT,
  267. PMUX_FUNC_HDMI,
  268. PMUX_FUNC_I2C1,
  269. PMUX_FUNC_I2C2,
  270. PMUX_FUNC_I2C3,
  271. PMUX_FUNC_IDE,
  272. PMUX_FUNC_KBC,
  273. PMUX_FUNC_MIO,
  274. PMUX_FUNC_MIPI_HS,
  275. PMUX_FUNC_NAND,
  276. PMUX_FUNC_OSC,
  277. PMUX_FUNC_OWR,
  278. PMUX_FUNC_PCIE,
  279. PMUX_FUNC_PLLA_OUT,
  280. PMUX_FUNC_PLLC_OUT1,
  281. PMUX_FUNC_PLLM_OUT1,
  282. PMUX_FUNC_PLLP_OUT2,
  283. PMUX_FUNC_PLLP_OUT3,
  284. PMUX_FUNC_PLLP_OUT4,
  285. PMUX_FUNC_PWM,
  286. PMUX_FUNC_PWR_INTR,
  287. PMUX_FUNC_PWR_ON,
  288. PMUX_FUNC_RTCK,
  289. PMUX_FUNC_SDMMC1,
  290. PMUX_FUNC_SDMMC2,
  291. PMUX_FUNC_SDMMC3,
  292. PMUX_FUNC_SDMMC4,
  293. PMUX_FUNC_SFLASH,
  294. PMUX_FUNC_SPDIF,
  295. PMUX_FUNC_SPI1,
  296. PMUX_FUNC_SPI2,
  297. PMUX_FUNC_SPI2_ALT,
  298. PMUX_FUNC_SPI3,
  299. PMUX_FUNC_SPI4,
  300. PMUX_FUNC_TRACE,
  301. PMUX_FUNC_TWC,
  302. PMUX_FUNC_UARTA,
  303. PMUX_FUNC_UARTB,
  304. PMUX_FUNC_UARTC,
  305. PMUX_FUNC_UARTD,
  306. PMUX_FUNC_UARTE,
  307. PMUX_FUNC_ULPI,
  308. PMUX_FUNC_VI,
  309. PMUX_FUNC_VI_SENSOR_CLK,
  310. PMUX_FUNC_XIO,
  311. /* End of Tegra2 MUX selectors */
  312. PMUX_FUNC_BLINK,
  313. PMUX_FUNC_CEC,
  314. PMUX_FUNC_CLK12,
  315. PMUX_FUNC_DAP,
  316. PMUX_FUNC_DAPSDMMC2,
  317. PMUX_FUNC_DDR,
  318. PMUX_FUNC_DEV3,
  319. PMUX_FUNC_DTV,
  320. PMUX_FUNC_VI_ALT1,
  321. PMUX_FUNC_VI_ALT2,
  322. PMUX_FUNC_VI_ALT3,
  323. PMUX_FUNC_EMC_DLL,
  324. PMUX_FUNC_EXTPERIPH1,
  325. PMUX_FUNC_EXTPERIPH2,
  326. PMUX_FUNC_EXTPERIPH3,
  327. PMUX_FUNC_GMI_ALT,
  328. PMUX_FUNC_HDA,
  329. PMUX_FUNC_HSI,
  330. PMUX_FUNC_I2C4,
  331. PMUX_FUNC_I2C5,
  332. PMUX_FUNC_I2CPWR,
  333. PMUX_FUNC_I2S0,
  334. PMUX_FUNC_I2S1,
  335. PMUX_FUNC_I2S2,
  336. PMUX_FUNC_I2S3,
  337. PMUX_FUNC_I2S4,
  338. PMUX_FUNC_NAND_ALT,
  339. PMUX_FUNC_POPSDIO4,
  340. PMUX_FUNC_POPSDMMC4,
  341. PMUX_FUNC_PWM0,
  342. PMUX_FUNC_PWM1,
  343. PMUX_FUNC_PWM2,
  344. PMUX_FUNC_PWM3,
  345. PMUX_FUNC_SATA,
  346. PMUX_FUNC_SPI5,
  347. PMUX_FUNC_SPI6,
  348. PMUX_FUNC_SYSCLK,
  349. PMUX_FUNC_VGP1,
  350. PMUX_FUNC_VGP2,
  351. PMUX_FUNC_VGP3,
  352. PMUX_FUNC_VGP4,
  353. PMUX_FUNC_VGP5,
  354. PMUX_FUNC_VGP6,
  355. /* End of Tegra3 MUX selectors */
  356. PMUX_FUNC_USB,
  357. PMUX_FUNC_SOC,
  358. PMUX_FUNC_CPU,
  359. PMUX_FUNC_CLK,
  360. PMUX_FUNC_PWRON,
  361. PMUX_FUNC_PMI,
  362. PMUX_FUNC_CLDVFS,
  363. PMUX_FUNC_RESET_OUT_N,
  364. /* End of Tegra114 MUX selectors */
  365. PMUX_FUNC_SAFE,
  366. PMUX_FUNC_MAX,
  367. PMUX_FUNC_INVALID = 0x4000,
  368. PMUX_FUNC_RSVD1 = 0x8000,
  369. PMUX_FUNC_RSVD2 = 0x8001,
  370. PMUX_FUNC_RSVD3 = 0x8002,
  371. PMUX_FUNC_RSVD4 = 0x8003,
  372. };
  373. /* return 1 if a pmux_func is in range */
  374. #define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
  375. || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
  376. /* return 1 if a pingrp is in range */
  377. #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
  378. /* The pullup/pulldown state of a pin group */
  379. enum pmux_pull {
  380. PMUX_PULL_NORMAL = 0,
  381. PMUX_PULL_DOWN,
  382. PMUX_PULL_UP,
  383. };
  384. /* return 1 if a pin_pupd_is in range */
  385. #define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
  386. ((pupd) <= PMUX_PULL_UP))
  387. /* Defines whether a pin group is tristated or in normal operation */
  388. enum pmux_tristate {
  389. PMUX_TRI_NORMAL = 0,
  390. PMUX_TRI_TRISTATE = 1,
  391. };
  392. /* return 1 if a pin_tristate_is in range */
  393. #define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
  394. && ((tristate) <= PMUX_TRI_TRISTATE))
  395. enum pmux_pin_io {
  396. PMUX_PIN_OUTPUT = 0,
  397. PMUX_PIN_INPUT = 1,
  398. PMUX_PIN_NONE,
  399. };
  400. /* return 1 if a pin_io_is in range */
  401. #define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
  402. ((io) <= PMUX_PIN_INPUT))
  403. enum pmux_pin_lock {
  404. PMUX_PIN_LOCK_DEFAULT = 0,
  405. PMUX_PIN_LOCK_DISABLE,
  406. PMUX_PIN_LOCK_ENABLE,
  407. };
  408. /* return 1 if a pin_lock is in range */
  409. #define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
  410. ((lock) <= PMUX_PIN_LOCK_ENABLE))
  411. enum pmux_pin_od {
  412. PMUX_PIN_OD_DEFAULT = 0,
  413. PMUX_PIN_OD_DISABLE,
  414. PMUX_PIN_OD_ENABLE,
  415. };
  416. /* return 1 if a pin_od is in range */
  417. #define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
  418. ((od) <= PMUX_PIN_OD_ENABLE))
  419. enum pmux_pin_ioreset {
  420. PMUX_PIN_IO_RESET_DEFAULT = 0,
  421. PMUX_PIN_IO_RESET_DISABLE,
  422. PMUX_PIN_IO_RESET_ENABLE,
  423. };
  424. /* return 1 if a pin_ioreset_is in range */
  425. #define pmux_pin_ioreset_isvalid(ioreset) \
  426. (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
  427. ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
  428. enum pmux_pin_rcv_sel {
  429. PMUX_PIN_RCV_SEL_DEFAULT = 0,
  430. PMUX_PIN_RCV_SEL_NORMAL,
  431. PMUX_PIN_RCV_SEL_HIGH,
  432. };
  433. /* return 1 if a pin_rcv_sel_is in range */
  434. #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
  435. (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
  436. ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
  437. /* Available power domains used by pin groups */
  438. enum pmux_vddio {
  439. PMUX_VDDIO_BB = 0,
  440. PMUX_VDDIO_LCD,
  441. PMUX_VDDIO_VI,
  442. PMUX_VDDIO_UART,
  443. PMUX_VDDIO_DDR,
  444. PMUX_VDDIO_NAND,
  445. PMUX_VDDIO_SYS,
  446. PMUX_VDDIO_AUDIO,
  447. PMUX_VDDIO_SD,
  448. PMUX_VDDIO_CAM,
  449. PMUX_VDDIO_GMI,
  450. PMUX_VDDIO_PEXCTL,
  451. PMUX_VDDIO_SDMMC1,
  452. PMUX_VDDIO_SDMMC3,
  453. PMUX_VDDIO_SDMMC4,
  454. PMUX_VDDIO_NONE
  455. };
  456. #define PGRP_SLWF_NONE -1
  457. #define PGRP_SLWF_MAX 3
  458. #define PGRP_SLWR_NONE PGRP_SLWF_NONE
  459. #define PGRP_SLWR_MAX PGRP_SLWF_MAX
  460. #define PGRP_DRVUP_NONE -1
  461. #define PGRP_DRVUP_MAX 127
  462. #define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
  463. #define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
  464. #define PGRP_SCHMT_NONE -1
  465. #define PGRP_HSM_NONE PGRP_SCHMT_NONE
  466. /* return 1 if a padgrp is in range */
  467. #define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
  468. /* return 1 if a slew-rate rising/falling edge value is in range */
  469. #define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
  470. (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
  471. /* return 1 if a driver output pull-up/down strength code value is in range */
  472. #define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
  473. (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
  474. /* return 1 if a low-power mode value is in range */
  475. #define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
  476. (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
  477. /* Defines a pin group cfg's low-power mode select */
  478. enum pgrp_lpmd {
  479. PGRP_LPMD_X8 = 0,
  480. PGRP_LPMD_X4,
  481. PGRP_LPMD_X2,
  482. PGRP_LPMD_X,
  483. PGRP_LPMD_NONE = -1,
  484. };
  485. /* Defines whether a pin group cfg's schmidt is enabled or not */
  486. enum pgrp_schmt {
  487. PGRP_SCHMT_DISABLE = 0,
  488. PGRP_SCHMT_ENABLE = 1,
  489. };
  490. /* Defines whether a pin group cfg's high-speed mode is enabled or not */
  491. enum pgrp_hsm {
  492. PGRP_HSM_DISABLE = 0,
  493. PGRP_HSM_ENABLE = 1,
  494. };
  495. /*
  496. * This defines the configuration for a pin group's pad control config
  497. */
  498. struct padctrl_config {
  499. enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
  500. int slwf; /* falling edge slew */
  501. int slwr; /* rising edge slew */
  502. int drvup; /* pull-up drive strength */
  503. int drvdn; /* pull-down drive strength */
  504. enum pgrp_lpmd lpmd; /* low-power mode selection */
  505. enum pgrp_schmt schmt; /* schmidt enable */
  506. enum pgrp_hsm hsm; /* high-speed mode enable */
  507. };
  508. /* t114 pin drive group and pin mux registers */
  509. #define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
  510. #define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
  511. PDRIVE_PINGROUP_COUNT)
  512. struct pmux_tri_ctlr {
  513. uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
  514. uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
  515. uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
  516. uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
  517. uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
  518. uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
  519. uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
  520. uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
  521. uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
  522. uint pmt_reserved5[PMUX_OFFSET];
  523. uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
  524. };
  525. /*
  526. * This defines the configuration for a pin, including the function assigned,
  527. * pull up/down settings and tristate settings. Having set up one of these
  528. * you can call pinmux_config_pingroup() to configure a pin in one step. Also
  529. * available is pinmux_config_table() to configure a list of pins.
  530. */
  531. struct pingroup_config {
  532. enum pmux_pingrp pingroup; /* pin group PINGRP_... */
  533. enum pmux_func func; /* function to assign FUNC_... */
  534. enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
  535. enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
  536. enum pmux_pin_io io; /* input or output PMUX_PIN_... */
  537. enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
  538. enum pmux_pin_od od; /* open-drain or push-pull driver */
  539. enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
  540. enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
  541. /* VIL/VIH receivers */
  542. };
  543. /* Set a pin group to tristate */
  544. void pinmux_tristate_enable(enum pmux_pingrp pin);
  545. /* Set a pin group to normal (non tristate) */
  546. void pinmux_tristate_disable(enum pmux_pingrp pin);
  547. /* Set the pull up/down feature for a pin group */
  548. void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
  549. /* Set the mux function for a pin group */
  550. void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
  551. /* Set the complete configuration for a pin group */
  552. void pinmux_config_pingroup(struct pingroup_config *config);
  553. /* Set a pin group to tristate or normal */
  554. void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
  555. /* Set a pin group as input or output */
  556. void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
  557. /**
  558. * Configure a list of pin groups
  559. *
  560. * @param config List of config items
  561. * @param len Number of config items in list
  562. */
  563. void pinmux_config_table(struct pingroup_config *config, int len);
  564. /* Set a group of pins from a table */
  565. void pinmux_init(void);
  566. /**
  567. * Set the GP pad configs
  568. *
  569. * @param config List of config items
  570. * @param len Number of config items in list
  571. */
  572. void padgrp_config_table(struct padctrl_config *config, int len);
  573. #endif /* _TEGRA114_PINMUX_H_ */