usb.h 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249
  1. /*
  2. * Copyright (c) 2011 The Chromium OS Authors.
  3. * See file CREDITS for list of people who contributed to this
  4. * project.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of
  9. * the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19. * MA 02111-1307 USA
  20. */
  21. #ifndef _TEGRA_USB_H_
  22. #define _TEGRA_USB_H_
  23. /* USB Controller (USBx_CONTROLLER_) regs */
  24. struct usb_ctlr {
  25. /* 0x000 */
  26. uint id;
  27. uint reserved0;
  28. uint host;
  29. uint device;
  30. /* 0x010 */
  31. uint txbuf;
  32. uint rxbuf;
  33. uint reserved1[2];
  34. /* 0x020 */
  35. uint reserved2[56];
  36. /* 0x100 */
  37. u16 cap_length;
  38. u16 hci_version;
  39. uint hcs_params;
  40. uint hcc_params;
  41. uint reserved3[5];
  42. /* 0x120 */
  43. uint dci_version;
  44. uint dcc_params;
  45. uint reserved4[6];
  46. /* 0x140 */
  47. uint usb_cmd;
  48. uint usb_sts;
  49. uint usb_intr;
  50. uint frindex;
  51. /* 0x150 */
  52. uint reserved5;
  53. uint periodic_list_base;
  54. uint async_list_addr;
  55. uint async_tt_sts;
  56. /* 0x160 */
  57. uint burst_size;
  58. uint tx_fill_tuning;
  59. uint reserved6; /* is this port_sc1 on some controllers? */
  60. uint icusb_ctrl;
  61. /* 0x170 */
  62. uint ulpi_viewport;
  63. uint reserved7;
  64. uint endpt_nak;
  65. uint endpt_nak_enable;
  66. /* 0x180 */
  67. uint reserved;
  68. uint port_sc1;
  69. uint reserved8[6];
  70. /* 0x1a0 */
  71. uint reserved9;
  72. uint otgsc;
  73. uint usb_mode;
  74. uint endpt_setup_stat;
  75. /* 0x1b0 */
  76. uint reserved10[20];
  77. /* 0x200 */
  78. uint reserved11[0x80];
  79. /* 0x400 */
  80. uint susp_ctrl;
  81. uint phy_vbus_sensors;
  82. uint phy_vbus_wakeup_id;
  83. uint phy_alt_vbus_sys;
  84. /* 0x410 */
  85. uint usb1_legacy_ctrl;
  86. uint reserved12[4];
  87. /* 0x424 */
  88. uint ulpi_timing_ctrl_0;
  89. uint ulpi_timing_ctrl_1;
  90. uint reserved13[53];
  91. /* 0x500 */
  92. uint reserved14[64 * 3];
  93. /* 0x800 */
  94. uint utmip_pll_cfg0;
  95. uint utmip_pll_cfg1;
  96. uint utmip_xcvr_cfg0;
  97. uint utmip_bias_cfg0;
  98. /* 0x810 */
  99. uint utmip_hsrx_cfg0;
  100. uint utmip_hsrx_cfg1;
  101. uint utmip_fslsrx_cfg0;
  102. uint utmip_fslsrx_cfg1;
  103. /* 0x820 */
  104. uint utmip_tx_cfg0;
  105. uint utmip_misc_cfg0;
  106. uint utmip_misc_cfg1;
  107. uint utmip_debounce_cfg0;
  108. /* 0x830 */
  109. uint utmip_bat_chrg_cfg0;
  110. uint utmip_spare_cfg0;
  111. uint utmip_xcvr_cfg1;
  112. uint utmip_bias_cfg1;
  113. };
  114. /* USB1_LEGACY_CTRL */
  115. #define USB1_NO_LEGACY_MODE 1
  116. #define VBUS_SENSE_CTL_SHIFT 1
  117. #define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
  118. #define VBUS_SENSE_CTL_VBUS_WAKEUP 0
  119. #define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
  120. #define VBUS_SENSE_CTL_AB_SESS_VLD 2
  121. #define VBUS_SENSE_CTL_A_SESS_VLD 3
  122. /* USB2_IF_ULPI_TIMING_CTRL_0 */
  123. #define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
  124. #define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
  125. /* USB2_IF_ULPI_TIMING_CTRL_1 */
  126. #define ULPI_DATA_TRIMMER_LOAD (1 << 0)
  127. #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
  128. #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
  129. #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
  130. #define ULPI_DIR_TRIMMER_LOAD (1 << 24)
  131. #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
  132. /* USBx_IF_USB_SUSP_CTRL_0 */
  133. #define ULPI_PHY_ENB (1 << 13)
  134. #define UTMIP_PHY_ENB (1 << 12)
  135. #define UTMIP_RESET (1 << 11)
  136. #define USB_PHY_CLK_VALID (1 << 7)
  137. #define USB_SUSP_CLR (1 << 5)
  138. /* USBx_UTMIP_MISC_CFG1 */
  139. #define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
  140. #define UTMIP_PLLU_STABLE_COUNT_MASK \
  141. (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
  142. #define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
  143. #define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
  144. (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
  145. #define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
  146. /* USBx_UTMIP_PLL_CFG1_0 */
  147. #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
  148. #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
  149. (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
  150. #define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
  151. #define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
  152. /* USBx_UTMIP_BIAS_CFG1_0 */
  153. #define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
  154. #define UTMIP_BIAS_PDTRK_COUNT_MASK \
  155. (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
  156. #define UTMIP_DEBOUNCE_CFG0_SHIFT 0
  157. #define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
  158. /* USBx_UTMIP_TX_CFG0_0 */
  159. #define UTMIP_FS_PREAMBLE_J (1 << 19)
  160. /* USBx_UTMIP_BAT_CHRG_CFG0_0 */
  161. #define UTMIP_PD_CHRG 1
  162. /* USBx_UTMIP_XCVR_CFG0_0 */
  163. #define UTMIP_XCVR_LSBIAS_SE (1 << 21)
  164. /* USBx_UTMIP_SPARE_CFG0_0 */
  165. #define FUSE_SETUP_SEL (1 << 3)
  166. /* USBx_UTMIP_HSRX_CFG0_0 */
  167. #define UTMIP_IDLE_WAIT_SHIFT 15
  168. #define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
  169. #define UTMIP_ELASTIC_LIMIT_SHIFT 10
  170. #define UTMIP_ELASTIC_LIMIT_MASK \
  171. (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
  172. /* USBx_UTMIP_HSRX_CFG0_1 */
  173. #define UTMIP_HS_SYNC_START_DLY_SHIFT 1
  174. #define UTMIP_HS_SYNC_START_DLY_MASK \
  175. (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT)
  176. /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
  177. #define IC_ENB1 (1 << 3)
  178. /* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
  179. #define PTS_SHIFT 30
  180. #define PTS_MASK (3U << PTS_SHIFT)
  181. #define PTS_UTMI 0
  182. #define PTS_RESERVED 1
  183. #define PTS_ULPI 2
  184. #define PTS_ICUSB_SER 3
  185. #define STS (1 << 29)
  186. #define WKOC (1 << 22)
  187. #define WKDS (1 << 21)
  188. #define WKCN (1 << 20)
  189. /* USBx_UTMIP_XCVR_CFG0_0 */
  190. #define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
  191. #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
  192. #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
  193. /* USBx_UTMIP_XCVR_CFG1_0 */
  194. #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
  195. #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
  196. #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
  197. /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
  198. #define VBUS_VLD_STS (1 << 26)
  199. /* Setup USB on the board */
  200. int board_usb_init(const void *blob);
  201. #endif /* _TEGRA_USB_H_ */