tegra_mmc.h 6.8 KB

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  1. /*
  2. * (C) Copyright 2009 SAMSUNG Electronics
  3. * Minkyu Kang <mk7.kang@samsung.com>
  4. * Portions Copyright (C) 2011-2012 NVIDIA Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #ifndef __TEGRA_MMC_H_
  22. #define __TEGRA_MMC_H_
  23. #include <fdtdec.h>
  24. #define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */
  25. #ifndef __ASSEMBLY__
  26. struct tegra_mmc {
  27. unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
  28. unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
  29. unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
  30. unsigned int argument; /* _ARGUMENT_0 */
  31. unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */
  32. unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */
  33. unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
  34. unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
  35. unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
  36. unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
  37. unsigned int bdata; /* _BUFFER_DATA_PORT_0 */
  38. unsigned int prnsts; /* _PRESENT_STATE_0 */
  39. unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */
  40. unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */
  41. unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */
  42. unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */
  43. unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */
  44. unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */
  45. unsigned char swrst; /* _SW_RESET_ 31:24 */
  46. unsigned int norintsts; /* _INTERRUPT_STATUS_0 */
  47. unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */
  48. unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */
  49. unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
  50. unsigned char res1[2]; /* _RESERVED 31:16 */
  51. unsigned int capareg; /* _CAPABILITIES_0 */
  52. unsigned char res2[4]; /* RESERVED, offset 44h-47h */
  53. unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */
  54. unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */
  55. unsigned short setacmd12err; /* offset 50h */
  56. unsigned short setinterr; /* offset 52h */
  57. unsigned char admaerr; /* offset 54h */
  58. unsigned char res4[3]; /* RESERVED, offset 55h-57h */
  59. unsigned long admaaddr; /* offset 58h-5Fh */
  60. unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
  61. unsigned short slotintstatus; /* offset FCh */
  62. unsigned short hcver; /* HOST Version */
  63. unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */
  64. unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */
  65. unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */
  66. unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */
  67. unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */
  68. unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */
  69. unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */
  70. unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */
  71. unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */
  72. unsigned int res6[47]; /* 0x124 ~ 0x1DC */
  73. unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */
  74. unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */
  75. unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */
  76. unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */
  77. };
  78. #define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0)
  79. #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1)
  80. #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1)
  81. #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1)
  82. #define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
  83. #define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
  84. #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
  85. #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3)
  86. #define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0)
  87. #define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1)
  88. #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4)
  89. #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4)
  90. #define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5)
  91. #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0)
  92. #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0)
  93. #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0)
  94. #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0)
  95. #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0)
  96. #define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3)
  97. #define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4)
  98. #define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5)
  99. #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0)
  100. #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1)
  101. #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0)
  102. #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1)
  103. #define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2)
  104. #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8
  105. #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
  106. #define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
  107. #define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1)
  108. #define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2)
  109. #define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0)
  110. #define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1)
  111. #define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3)
  112. #define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15)
  113. #define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16)
  114. #define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0)
  115. #define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1)
  116. #define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3)
  117. #define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4)
  118. #define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5)
  119. #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
  120. /* SDMMC1/3 settings from section 24.6 of T30 TRM */
  121. #define MEMCOMP_PADCTRL_VREF 7
  122. #define AUTO_CAL_ENABLED (1 << 29)
  123. #define AUTO_CAL_PD_OFFSET (0x70 << 8)
  124. #define AUTO_CAL_PU_OFFSET (0x62 << 0)
  125. struct mmc_host {
  126. struct tegra_mmc *reg;
  127. int id; /* device id/number, 0-3 */
  128. int enabled; /* 1 to enable, 0 to disable */
  129. int width; /* Bus Width, 1, 4 or 8 */
  130. enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
  131. struct fdt_gpio_state cd_gpio; /* Change Detect GPIO */
  132. struct fdt_gpio_state pwr_gpio; /* Power GPIO */
  133. struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */
  134. unsigned int version; /* SDHCI spec. version */
  135. unsigned int clock; /* Current clock (MHz) */
  136. };
  137. void pad_init_mmc(struct mmc_host *host);
  138. #endif /* __ASSEMBLY__ */
  139. #endif /* __TEGRA_MMC_H_ */