tegra_i2c.h 5.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170
  1. /*
  2. * NVIDIA Tegra I2C controller
  3. *
  4. * Copyright 2010-2011 NVIDIA Corporation
  5. *
  6. * This software may be used and distributed according to the
  7. * terms of the GNU Public License, Version 2, incorporated
  8. * herein by reference.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License
  12. * Version 2 as published by the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #ifndef _TEGRA_I2C_H_
  25. #define _TEGRA_I2C_H_
  26. #include <asm/types.h>
  27. enum {
  28. I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */
  29. I2C_FIFO_DEPTH = 8, /* I2C fifo depth */
  30. };
  31. enum i2c_transaction_flags {
  32. I2C_IS_WRITE = 0x1, /* for I2C write operation */
  33. I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */
  34. I2C_USE_REPEATED_START = 0x4, /* for repeat start */
  35. I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */
  36. I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */
  37. I2C_NO_STOP = 0x20,
  38. };
  39. /* Contians the I2C transaction details */
  40. struct i2c_trans_info {
  41. /* flags to indicate the transaction details */
  42. enum i2c_transaction_flags flags;
  43. u32 address; /* I2C slave device address */
  44. u32 num_bytes; /* number of bytes to be transferred */
  45. /*
  46. * Send/receive buffer. For the I2C send operation this buffer should
  47. * be filled with the data to be sent to the slave device. For the I2C
  48. * receive operation this buffer is filled with the data received from
  49. * the slave device.
  50. */
  51. u8 *buf;
  52. int is_10bit_address;
  53. };
  54. struct i2c_control {
  55. u32 tx_fifo;
  56. u32 rx_fifo;
  57. u32 packet_status;
  58. u32 fifo_control;
  59. u32 fifo_status;
  60. u32 int_mask;
  61. u32 int_status;
  62. };
  63. struct dvc_ctlr {
  64. u32 ctrl1; /* 00: DVC_CTRL_REG1 */
  65. u32 ctrl2; /* 04: DVC_CTRL_REG2 */
  66. u32 ctrl3; /* 08: DVC_CTRL_REG3 */
  67. u32 status; /* 0C: DVC_STATUS_REG */
  68. u32 ctrl; /* 10: DVC_I2C_CTRL_REG */
  69. u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */
  70. u32 reserved_0[2]; /* 18: */
  71. u32 req; /* 20: DVC_REQ_REGISTER */
  72. u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */
  73. u32 reserved_1[6]; /* 28: */
  74. u32 cnfg; /* 40: DVC_I2C_CNFG */
  75. u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */
  76. u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */
  77. u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */
  78. u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */
  79. u32 reserved_2[2]; /* 54: */
  80. u32 i2c_status; /* 5C: DVC_I2C_STATUS */
  81. struct i2c_control control; /* 60 ~ 78 */
  82. };
  83. struct i2c_ctlr {
  84. u32 cnfg; /* 00: I2C_I2C_CNFG */
  85. u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */
  86. u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */
  87. u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */
  88. u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */
  89. u32 reserved_0[2]; /* 14: */
  90. u32 status; /* 1C: I2C_I2C_STATUS */
  91. u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */
  92. u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */
  93. u32 sl_status; /* 28: I2C_I2C_SL_STATUS */
  94. u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */
  95. u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */
  96. u32 reserved_1[2]; /* 34: */
  97. u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */
  98. u32 reserved_2[4]; /* 40: */
  99. struct i2c_control control; /* 50 ~ 68 */
  100. u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */
  101. };
  102. /* bit fields definitions for IO Packet Header 1 format */
  103. #define PKT_HDR1_PROTOCOL_SHIFT 4
  104. #define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT)
  105. #define PKT_HDR1_CTLR_ID_SHIFT 12
  106. #define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT)
  107. #define PKT_HDR1_PKT_ID_SHIFT 16
  108. #define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT)
  109. #define PROTOCOL_TYPE_I2C 1
  110. /* bit fields definitions for IO Packet Header 2 format */
  111. #define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0
  112. #define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT)
  113. /* bit fields definitions for IO Packet Header 3 format */
  114. #define PKT_HDR3_READ_MODE_SHIFT 19
  115. #define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT)
  116. #define PKT_HDR3_SLAVE_ADDR_SHIFT 0
  117. #define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
  118. #define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26
  119. #define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \
  120. (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT)
  121. /* I2C_CNFG */
  122. #define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11
  123. #define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT)
  124. #define I2C_CNFG_PACKET_MODE_SHIFT 10
  125. #define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT)
  126. /* I2C_SL_CNFG */
  127. #define I2C_SL_CNFG_NEWSL_SHIFT 2
  128. #define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT)
  129. /* I2C_FIFO_STATUS */
  130. #define TX_FIFO_FULL_CNT_SHIFT 0
  131. #define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT)
  132. #define TX_FIFO_EMPTY_CNT_SHIFT 4
  133. #define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT)
  134. /* I2C_INTERRUPT_STATUS */
  135. #define I2C_INT_XFER_COMPLETE_SHIFT 7
  136. #define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT)
  137. #define I2C_INT_NO_ACK_SHIFT 3
  138. #define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT)
  139. #define I2C_INT_ARBITRATION_LOST_SHIFT 2
  140. #define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
  141. /* I2C_CLK_DIVISOR_REGISTER */
  142. #define CLK_DIV_STD_FAST_MODE 0x19
  143. #define CLK_DIV_HS_MODE 1
  144. #define CLK_MULT_STD_FAST_MODE 8
  145. /**
  146. * Returns the bus number of the DVC controller
  147. *
  148. * @return number of bus, or -1 if there is no DVC active
  149. */
  150. int tegra_i2c_get_dvc_bus_num(void);
  151. #endif /* _TEGRA_I2C_H_ */