omap.h 8.2 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Authors:
  6. * Aneesh V <aneesh@ti.com>
  7. * Sricharan R <r.sricharan@ti.com>
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #ifndef _OMAP5_H_
  28. #define _OMAP5_H_
  29. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  30. #include <asm/types.h>
  31. #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  32. /*
  33. * L4 Peripherals - L4 Wakeup and L4 Core now
  34. */
  35. #define OMAP54XX_L4_CORE_BASE 0x4A000000
  36. #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
  37. #define OMAP54XX_L4_PER_BASE 0x48000000
  38. #define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
  39. #define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF
  40. #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
  41. #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
  42. /* CONTROL */
  43. #define CTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
  44. #define CONTROL_PADCONF_CORE (CTRL_BASE + 0x0800)
  45. #define CONTROL_PADCONF_WKUP (OMAP54XX_L4_WKUP_BASE + 0xc800)
  46. /* LPDDR2 IO regs. To be verified */
  47. #define LPDDR2_IO_REGS_BASE 0x4A100638
  48. /* CONTROL_ID_CODE */
  49. #define CONTROL_ID_CODE (CTRL_BASE + 0x204)
  50. /* To be verified */
  51. #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
  52. #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
  53. #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
  54. #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
  55. #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
  56. /* STD_FUSE_PROD_ID_1 */
  57. #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
  58. #define PROD_ID_1_SILICON_TYPE_SHIFT 16
  59. #define PROD_ID_1_SILICON_TYPE_MASK (3 << 16)
  60. /* UART */
  61. #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
  62. #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
  63. #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
  64. /* General Purpose Timers */
  65. #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
  66. #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000)
  67. #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000)
  68. /* Watchdog Timer2 - MPU watchdog */
  69. #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
  70. /* 32KTIMER */
  71. #define SYNC_32KTIMER_BASE (OMAP54XX_L4_WKUP_BASE + 0x4000)
  72. /* GPMC */
  73. #define OMAP54XX_GPMC_BASE 0x50000000
  74. /* SYSTEM CONTROL MODULE */
  75. #define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
  76. /*
  77. * Hardware Register Details
  78. */
  79. /* Watchdog Timer */
  80. #define WD_UNLOCK1 0xAAAA
  81. #define WD_UNLOCK2 0x5555
  82. /* GP Timer */
  83. #define TCLR_ST (0x1 << 0)
  84. #define TCLR_AR (0x1 << 1)
  85. #define TCLR_PRE (0x1 << 5)
  86. /* Control Module */
  87. #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
  88. #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
  89. #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
  90. #define CONTROL_EFUSE_2_OVERRIDE 0x00084000
  91. /* LPDDR2 IO regs */
  92. #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
  93. #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
  94. #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
  95. #define LPDDR2IO_GR10_WD_MASK (3 << 17)
  96. #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
  97. /* CONTROL_EFUSE_2 */
  98. #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
  99. #define SDCARD_PWRDNZ (1 << 26)
  100. #define SDCARD_BIAS_HIZ_MODE (1 << 25)
  101. #define SDCARD_BIAS_PWRDNZ (1 << 22)
  102. #define SDCARD_PBIASLITE_VMODE (1 << 21)
  103. #ifndef __ASSEMBLY__
  104. struct s32ktimer {
  105. unsigned char res[0x10];
  106. unsigned int s32k_cr; /* 0x10 */
  107. };
  108. #define DEVICE_TYPE_SHIFT 0x6
  109. #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
  110. #define DEVICE_GP 0x3
  111. /* Output impedance control */
  112. #define ds_120_ohm 0x0
  113. #define ds_60_ohm 0x1
  114. #define ds_45_ohm 0x2
  115. #define ds_30_ohm 0x3
  116. #define ds_mask 0x3
  117. /* Slew rate control */
  118. #define sc_slow 0x0
  119. #define sc_medium 0x1
  120. #define sc_fast 0x2
  121. #define sc_na 0x3
  122. #define sc_mask 0x3
  123. /* Target capacitance control */
  124. #define lb_5_12_pf 0x0
  125. #define lb_12_25_pf 0x1
  126. #define lb_25_50_pf 0x2
  127. #define lb_50_80_pf 0x3
  128. #define lb_mask 0x3
  129. #define usb_i_mask 0x7
  130. #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082
  131. #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
  132. #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
  133. #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
  134. #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
  135. #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C
  136. #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464
  137. #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631
  138. #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
  139. #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
  140. #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
  141. #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
  142. #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
  143. #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
  144. #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
  145. #define EFUSE_1 0x45145100
  146. #define EFUSE_2 0x45145100
  147. #define EFUSE_3 0x45145100
  148. #define EFUSE_4 0x45145100
  149. #endif /* __ASSEMBLY__ */
  150. /*
  151. * Non-secure SRAM Addresses
  152. * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
  153. * at 0x40304000(EMU base) so that our code works for both EMU and GP
  154. */
  155. #define NON_SECURE_SRAM_START 0x40300000
  156. #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
  157. /* base address for indirect vectors (internal boot mode) */
  158. #define SRAM_ROM_VECT_BASE 0x4031F000
  159. #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
  160. /*
  161. * SRAM scratch space entries
  162. */
  163. #define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR
  164. #define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
  165. #define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
  166. #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
  167. #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
  168. #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
  169. #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
  170. #define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
  171. #define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
  172. /* Silicon revisions */
  173. #define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
  174. #define OMAP4430_ES1_0 0x44300100
  175. #define OMAP4430_ES2_0 0x44300200
  176. #define OMAP4430_ES2_1 0x44300210
  177. #define OMAP4430_ES2_2 0x44300220
  178. #define OMAP4430_ES2_3 0x44300230
  179. #define OMAP4460_ES1_0 0x44600100
  180. #define OMAP4460_ES1_1 0x44600110
  181. /* ROM code defines */
  182. /* Boot device */
  183. #define BOOT_DEVICE_MASK 0xFF
  184. #define BOOT_DEVICE_OFFSET 0x8
  185. #define DEV_DESC_PTR_OFFSET 0x4
  186. #define DEV_DATA_PTR_OFFSET 0x18
  187. #define BOOT_MODE_OFFSET 0x8
  188. #define RESET_REASON_OFFSET 0x9
  189. #define CH_FLAGS_OFFSET 0xA
  190. #define CH_FLAGS_CHSETTINGS (0x1 << 0)
  191. #define CH_FLAGS_CHRAM (0x1 << 1)
  192. #define CH_FLAGS_CHFLASH (0x1 << 2)
  193. #define CH_FLAGS_CHMMCSD (0x1 << 3)
  194. /* CONTROL_SRCOMP_XXX_SIDE */
  195. #define OVERRIDE_XS_SHIFT 30
  196. #define OVERRIDE_XS_MASK (1 << 30)
  197. #define SRCODE_READ_XS_SHIFT 12
  198. #define SRCODE_READ_XS_MASK (0xff << 12)
  199. #define PWRDWN_XS_SHIFT 11
  200. #define PWRDWN_XS_MASK (1 << 11)
  201. #define DIVIDE_FACTOR_XS_SHIFT 4
  202. #define DIVIDE_FACTOR_XS_MASK (0x7f << 4)
  203. #define MULTIPLY_FACTOR_XS_SHIFT 1
  204. #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1)
  205. #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
  206. #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
  207. #ifndef __ASSEMBLY__
  208. struct srcomp_params {
  209. s8 divide_factor;
  210. s8 multiply_factor;
  211. };
  212. struct omap_boot_parameters {
  213. char *boot_message;
  214. unsigned int mem_boot_descriptor;
  215. unsigned char omap_bootdevice;
  216. unsigned char reset_reason;
  217. unsigned char ch_flags;
  218. };
  219. struct ctrl_ioregs {
  220. u32 ctrl_ddrch;
  221. u32 ctrl_lpddr2ch;
  222. u32 ctrl_ddr3ch;
  223. u32 ctrl_ddrio_0;
  224. u32 ctrl_ddrio_1;
  225. u32 ctrl_ddrio_2;
  226. u32 ctrl_emif_sdram_config_ext;
  227. };
  228. #endif /* __ASSEMBLY__ */
  229. #endif