mux_dra7xx.h 8.0 KB

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  1. /*
  2. * (C) Copyright 2013
  3. * Texas Instruments Incorporated
  4. *
  5. * Nishant Kamat <nskamat@ti.com>
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #ifndef _MUX_DRA7XX_H_
  27. #define _MUX_DRA7XX_H_
  28. #include <asm/types.h>
  29. #define IEN (1 << 18)
  30. #define IDIS (0 << 18)
  31. #define PTU (3 << 16)
  32. #define PTD (1 << 16)
  33. #define PEN (1 << 16)
  34. #define PDIS (0 << 16)
  35. #define WKEN (1 << 24)
  36. #define WKDIS (0 << 24)
  37. #define M0 0
  38. #define M1 1
  39. #define M2 2
  40. #define M3 3
  41. #define M4 4
  42. #define M5 5
  43. #define M6 6
  44. #define M7 7
  45. #define M8 8
  46. #define M9 9
  47. #define M10 10
  48. #define M11 11
  49. #define M12 12
  50. #define M13 13
  51. #define M14 14
  52. #define M15 15
  53. #define SAFE_MODE M15
  54. #define GPMC_AD0 0x000
  55. #define GPMC_AD1 0x004
  56. #define GPMC_AD2 0x008
  57. #define GPMC_AD3 0x00C
  58. #define GPMC_AD4 0x010
  59. #define GPMC_AD5 0x014
  60. #define GPMC_AD6 0x018
  61. #define GPMC_AD7 0x01C
  62. #define GPMC_AD8 0x020
  63. #define GPMC_AD9 0x024
  64. #define GPMC_AD10 0x028
  65. #define GPMC_AD11 0x02C
  66. #define GPMC_AD12 0x030
  67. #define GPMC_AD13 0x034
  68. #define GPMC_AD14 0x038
  69. #define GPMC_AD15 0x03C
  70. #define GPMC_A0 0x040
  71. #define GPMC_A1 0x044
  72. #define GPMC_A2 0x048
  73. #define GPMC_A3 0x04C
  74. #define GPMC_A4 0x050
  75. #define GPMC_A5 0x054
  76. #define GPMC_A6 0x058
  77. #define GPMC_A7 0x05C
  78. #define GPMC_A8 0x060
  79. #define GPMC_A9 0x064
  80. #define GPMC_A10 0x068
  81. #define GPMC_A11 0x06C
  82. #define GPMC_A12 0x070
  83. #define GPMC_A13 0x074
  84. #define GPMC_A14 0x078
  85. #define GPMC_A15 0x07C
  86. #define GPMC_A16 0x080
  87. #define GPMC_A17 0x084
  88. #define GPMC_A18 0x088
  89. #define GPMC_A19 0x08C
  90. #define GPMC_A20 0x090
  91. #define GPMC_A21 0x094
  92. #define GPMC_A22 0x098
  93. #define GPMC_A23 0x09C
  94. #define GPMC_A24 0x0A0
  95. #define GPMC_A25 0x0A4
  96. #define GPMC_A26 0x0A8
  97. #define GPMC_A27 0x0AC
  98. #define GPMC_CS1 0x0B0
  99. #define GPMC_CS0 0x0B4
  100. #define GPMC_CS2 0x0B8
  101. #define GPMC_CS3 0x0BC
  102. #define GPMC_CLK 0x0C0
  103. #define GPMC_ADVN_ALE 0x0C4
  104. #define GPMC_OEN_REN 0x0C8
  105. #define GPMC_WEN 0x0CC
  106. #define GPMC_BEN0 0x0D0
  107. #define GPMC_BEN1 0x0D4
  108. #define GPMC_WAIT0 0x0D8
  109. #define VIN1A_CLK0 0x0DC
  110. #define VIN1B_CLK1 0x0E0
  111. #define VIN1A_DE0 0x0E4
  112. #define VIN1A_FLD0 0x0E8
  113. #define VIN1A_HSYNC0 0x0EC
  114. #define VIN1A_VSYNC0 0x0F0
  115. #define VIN1A_D0 0x0F4
  116. #define VIN1A_D1 0x0F8
  117. #define VIN1A_D2 0x0FC
  118. #define VIN1A_D3 0x100
  119. #define VIN1A_D4 0x104
  120. #define VIN1A_D5 0x108
  121. #define VIN1A_D6 0x10C
  122. #define VIN1A_D7 0x110
  123. #define VIN1A_D8 0x114
  124. #define VIN1A_D9 0x118
  125. #define VIN1A_D10 0x11C
  126. #define VIN1A_D11 0x120
  127. #define VIN1A_D12 0x124
  128. #define VIN1A_D13 0x128
  129. #define VIN1A_D14 0x12C
  130. #define VIN1A_D15 0x130
  131. #define VIN1A_D16 0x134
  132. #define VIN1A_D17 0x138
  133. #define VIN1A_D18 0x13C
  134. #define VIN1A_D19 0x140
  135. #define VIN1A_D20 0x144
  136. #define VIN1A_D21 0x148
  137. #define VIN1A_D22 0x14C
  138. #define VIN1A_D23 0x150
  139. #define VIN2A_CLK0 0x154
  140. #define VIN2A_DE0 0x158
  141. #define VIN2A_FLD0 0x15C
  142. #define VIN2A_HSYNC0 0x160
  143. #define VIN2A_VSYNC0 0x164
  144. #define VIN2A_D0 0x168
  145. #define VIN2A_D1 0x16C
  146. #define VIN2A_D2 0x170
  147. #define VIN2A_D3 0x174
  148. #define VIN2A_D4 0x178
  149. #define VIN2A_D5 0x17C
  150. #define VIN2A_D6 0x180
  151. #define VIN2A_D7 0x184
  152. #define VIN2A_D8 0x188
  153. #define VIN2A_D9 0x18C
  154. #define VIN2A_D10 0x190
  155. #define VIN2A_D11 0x194
  156. #define VIN2A_D12 0x198
  157. #define VIN2A_D13 0x19C
  158. #define VIN2A_D14 0x1A0
  159. #define VIN2A_D15 0x1A4
  160. #define VIN2A_D16 0x1A8
  161. #define VIN2A_D17 0x1AC
  162. #define VIN2A_D18 0x1B0
  163. #define VIN2A_D19 0x1B4
  164. #define VIN2A_D20 0x1B8
  165. #define VIN2A_D21 0x1BC
  166. #define VIN2A_D22 0x1C0
  167. #define VIN2A_D23 0x1C4
  168. #define VOUT1_CLK 0x1C8
  169. #define VOUT1_DE 0x1CC
  170. #define VOUT1_FLD 0x1D0
  171. #define VOUT1_HSYNC 0x1D4
  172. #define VOUT1_VSYNC 0x1D8
  173. #define VOUT1_D0 0x1DC
  174. #define VOUT1_D1 0x1E0
  175. #define VOUT1_D2 0x1E4
  176. #define VOUT1_D3 0x1E8
  177. #define VOUT1_D4 0x1EC
  178. #define VOUT1_D5 0x1F0
  179. #define VOUT1_D6 0x1F4
  180. #define VOUT1_D7 0x1F8
  181. #define VOUT1_D8 0x1FC
  182. #define VOUT1_D9 0x200
  183. #define VOUT1_D10 0x204
  184. #define VOUT1_D11 0x208
  185. #define VOUT1_D12 0x20C
  186. #define VOUT1_D13 0x210
  187. #define VOUT1_D14 0x214
  188. #define VOUT1_D15 0x218
  189. #define VOUT1_D16 0x21C
  190. #define VOUT1_D17 0x220
  191. #define VOUT1_D18 0x224
  192. #define VOUT1_D19 0x228
  193. #define VOUT1_D20 0x22C
  194. #define VOUT1_D21 0x230
  195. #define VOUT1_D22 0x234
  196. #define VOUT1_D23 0x238
  197. #define MDIO_MCLK 0x23C
  198. #define MDIO_D 0x240
  199. #define RMII_MHZ_50_CLK 0x244
  200. #define UART3_RXD 0x248
  201. #define UART3_TXD 0x24C
  202. #define RGMII0_TXC 0x250
  203. #define RGMII0_TXCTL 0x254
  204. #define RGMII0_TXD3 0x258
  205. #define RGMII0_TXD2 0x25C
  206. #define RGMII0_TXD1 0x260
  207. #define RGMII0_TXD0 0x264
  208. #define RGMII0_RXC 0x268
  209. #define RGMII0_RXCTL 0x26C
  210. #define RGMII0_RXD3 0x270
  211. #define RGMII0_RXD2 0x274
  212. #define RGMII0_RXD1 0x278
  213. #define RGMII0_RXD0 0x27C
  214. #define USB1_DRVVBUS 0x280
  215. #define USB2_DRVVBUS 0x284
  216. #define GPIO6_14 0x288
  217. #define GPIO6_15 0x28C
  218. #define GPIO6_16 0x290
  219. #define XREF_CLK0 0x294
  220. #define XREF_CLK1 0x298
  221. #define XREF_CLK2 0x29C
  222. #define XREF_CLK3 0x2A0
  223. #define MCASP1_ACLKX 0x2A4
  224. #define MCASP1_FSX 0x2A8
  225. #define MCASP1_ACLKR 0x2AC
  226. #define MCASP1_FSR 0x2B0
  227. #define MCASP1_AXR0 0x2B4
  228. #define MCASP1_AXR1 0x2B8
  229. #define MCASP1_AXR2 0x2BC
  230. #define MCASP1_AXR3 0x2C0
  231. #define MCASP1_AXR4 0x2C4
  232. #define MCASP1_AXR5 0x2C8
  233. #define MCASP1_AXR6 0x2CC
  234. #define MCASP1_AXR7 0x2D0
  235. #define MCASP1_AXR8 0x2D4
  236. #define MCASP1_AXR9 0x2D8
  237. #define MCASP1_AXR10 0x2DC
  238. #define MCASP1_AXR11 0x2E0
  239. #define MCASP1_AXR12 0x2E4
  240. #define MCASP1_AXR13 0x2E8
  241. #define MCASP1_AXR14 0x2EC
  242. #define MCASP1_AXR15 0x2F0
  243. #define MCASP2_ACLKX 0x2F4
  244. #define MCASP2_FSX 0x2F8
  245. #define MCASP2_ACLKR 0x2FC
  246. #define MCASP2_FSR 0x300
  247. #define MCASP2_AXR0 0x304
  248. #define MCASP2_AXR1 0x308
  249. #define MCASP2_AXR2 0x30C
  250. #define MCASP2_AXR3 0x310
  251. #define MCASP2_AXR4 0x314
  252. #define MCASP2_AXR5 0x318
  253. #define MCASP2_AXR6 0x31C
  254. #define MCASP2_AXR7 0x320
  255. #define MCASP3_ACLKX 0x324
  256. #define MCASP3_FSX 0x328
  257. #define MCASP3_AXR0 0x32C
  258. #define MCASP3_AXR1 0x330
  259. #define MCASP4_ACLKX 0x334
  260. #define MCASP4_FSX 0x338
  261. #define MCASP4_AXR0 0x33C
  262. #define MCASP4_AXR1 0x340
  263. #define MCASP5_ACLKX 0x344
  264. #define MCASP5_FSX 0x348
  265. #define MCASP5_AXR0 0x34C
  266. #define MCASP5_AXR1 0x350
  267. #define MMC1_CLK 0x354
  268. #define MMC1_CMD 0x358
  269. #define MMC1_DAT0 0x35C
  270. #define MMC1_DAT1 0x360
  271. #define MMC1_DAT2 0x364
  272. #define MMC1_DAT3 0x368
  273. #define MMC1_SDCD 0x36C
  274. #define MMC1_SDWP 0x370
  275. #define GPIO6_10 0x374
  276. #define GPIO6_11 0x378
  277. #define MMC3_CLK 0x37C
  278. #define MMC3_CMD 0x380
  279. #define MMC3_DAT0 0x384
  280. #define MMC3_DAT1 0x388
  281. #define MMC3_DAT2 0x38C
  282. #define MMC3_DAT3 0x390
  283. #define MMC3_DAT4 0x394
  284. #define MMC3_DAT5 0x398
  285. #define MMC3_DAT6 0x39C
  286. #define MMC3_DAT7 0x3A0
  287. #define SPI1_SCLK 0x3A4
  288. #define SPI1_D1 0x3A8
  289. #define SPI1_D0 0x3AC
  290. #define SPI1_CS0 0x3B0
  291. #define SPI1_CS1 0x3B4
  292. #define SPI1_CS2 0x3B8
  293. #define SPI1_CS3 0x3BC
  294. #define SPI2_SCLK 0x3C0
  295. #define SPI2_D1 0x3C4
  296. #define SPI2_D0 0x3C8
  297. #define SPI2_CS0 0x3CC
  298. #define DCAN1_TX 0x3D0
  299. #define DCAN1_RX 0x3D4
  300. #define DCAN2_TX 0x3D8
  301. #define DCAN2_RX 0x3DC
  302. #define UART1_RXD 0x3E0
  303. #define UART1_TXD 0x3E4
  304. #define UART1_CTSN 0x3E8
  305. #define UART1_RTSN 0x3EC
  306. #define UART2_RXD 0x3F0
  307. #define UART2_TXD 0x3F4
  308. #define UART2_CTSN 0x3F8
  309. #define UART2_RTSN 0x3FC
  310. #define I2C1_SDA 0x400
  311. #define I2C1_SCL 0x404
  312. #define I2C2_SDA 0x408
  313. #define I2C2_SCL 0x40C
  314. #define I2C3_SDA 0x410
  315. #define I2C3_SCL 0x414
  316. #define WAKEUP0 0x418
  317. #define WAKEUP1 0x41C
  318. #define WAKEUP2 0x420
  319. #define WAKEUP3 0x424
  320. #define ON_OFF 0x428
  321. #define RTC_PORZ 0x42C
  322. #define TMS 0x430
  323. #define TDI 0x434
  324. #define TDO 0x438
  325. #define TCLK 0x43C
  326. #define TRSTN 0x440
  327. #define RTCK 0x444
  328. #define EMU0 0x448
  329. #define EMU1 0x44C
  330. #define EMU2 0x450
  331. #define EMU3 0x454
  332. #define EMU4 0x458
  333. #define RESETN 0x45C
  334. #define NMIN 0x460
  335. #define RSTOUTN 0x464
  336. #endif /* _MUX_DRA7XX_H_ */