omap.h 5.7 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Authors:
  6. * Aneesh V <aneesh@ti.com>
  7. *
  8. * Derived from OMAP3 work by
  9. * Richard Woodruff <r-woodruff2@ti.com>
  10. * Syed Mohammed Khasim <x0khasim@ti.com>
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #ifndef _OMAP4_H_
  31. #define _OMAP4_H_
  32. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  33. #include <asm/types.h>
  34. #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  35. /*
  36. * L4 Peripherals - L4 Wakeup and L4 Core now
  37. */
  38. #define OMAP44XX_L4_CORE_BASE 0x4A000000
  39. #define OMAP44XX_L4_WKUP_BASE 0x4A300000
  40. #define OMAP44XX_L4_PER_BASE 0x48000000
  41. #define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
  42. #define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
  43. #define DRAM_ADDR_SPACE_START OMAP44XX_DRAM_ADDR_SPACE_START
  44. #define DRAM_ADDR_SPACE_END OMAP44XX_DRAM_ADDR_SPACE_END
  45. /* CONTROL */
  46. #define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
  47. #define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
  48. #define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
  49. /* LPDDR2 IO regs */
  50. #define LPDDR2_IO_REGS_BASE 0x4A100638
  51. /* CONTROL_ID_CODE */
  52. #define CONTROL_ID_CODE 0x4A002204
  53. #define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
  54. #define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
  55. #define OMAP4_CONTROL_ID_CODE_ES2_1 0x3B95C02F
  56. #define OMAP4_CONTROL_ID_CODE_ES2_2 0x4B95C02F
  57. #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F
  58. #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
  59. #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
  60. /* UART */
  61. #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
  62. #define UART2_BASE (OMAP44XX_L4_PER_BASE + 0x6c000)
  63. #define UART3_BASE (OMAP44XX_L4_PER_BASE + 0x20000)
  64. /* General Purpose Timers */
  65. #define GPT1_BASE (OMAP44XX_L4_WKUP_BASE + 0x18000)
  66. #define GPT2_BASE (OMAP44XX_L4_PER_BASE + 0x32000)
  67. #define GPT3_BASE (OMAP44XX_L4_PER_BASE + 0x34000)
  68. /* Watchdog Timer2 - MPU watchdog */
  69. #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
  70. /* 32KTIMER */
  71. #define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
  72. /* GPMC */
  73. #define OMAP44XX_GPMC_BASE 0x50000000
  74. /* SYSTEM CONTROL MODULE */
  75. #define SYSCTRL_GENERAL_CORE_BASE 0x4A002000
  76. /*
  77. * Hardware Register Details
  78. */
  79. /* Watchdog Timer */
  80. #define WD_UNLOCK1 0xAAAA
  81. #define WD_UNLOCK2 0x5555
  82. /* GP Timer */
  83. #define TCLR_ST (0x1 << 0)
  84. #define TCLR_AR (0x1 << 1)
  85. #define TCLR_PRE (0x1 << 5)
  86. /* Control Module */
  87. #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
  88. #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
  89. #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
  90. #define CONTROL_EFUSE_2_OVERRIDE 0x99084000
  91. /* LPDDR2 IO regs */
  92. #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
  93. #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
  94. #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
  95. #define LPDDR2IO_GR10_WD_MASK (3 << 17)
  96. #define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F
  97. /* CONTROL_EFUSE_2 */
  98. #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
  99. #define MMC1_PWRDNZ (1 << 26)
  100. #define MMC1_PBIASLITE_PWRDNZ (1 << 22)
  101. #define MMC1_PBIASLITE_VMODE (1 << 21)
  102. #ifndef __ASSEMBLY__
  103. struct s32ktimer {
  104. unsigned char res[0x10];
  105. unsigned int s32k_cr; /* 0x10 */
  106. };
  107. #define DEVICE_TYPE_SHIFT (0x8)
  108. #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
  109. #define DEVICE_GP 0x3
  110. #endif /* __ASSEMBLY__ */
  111. /*
  112. * Non-secure SRAM Addresses
  113. * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
  114. * at 0x40304000(EMU base) so that our code works for both EMU and GP
  115. */
  116. #define NON_SECURE_SRAM_START 0x40304000
  117. #define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
  118. /* base address for indirect vectors (internal boot mode) */
  119. #define SRAM_ROM_VECT_BASE 0x4030D000
  120. /* Temporary SRAM stack used while low level init is done */
  121. #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
  122. /* SRAM scratch space entries */
  123. #define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR
  124. #define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
  125. #define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
  126. #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
  127. #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
  128. #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
  129. #define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
  130. #define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
  131. #define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
  132. /* ROM code defines */
  133. /* Boot device */
  134. #define BOOT_DEVICE_MASK 0xFF
  135. #define BOOT_DEVICE_OFFSET 0x8
  136. #define DEV_DESC_PTR_OFFSET 0x4
  137. #define DEV_DATA_PTR_OFFSET 0x18
  138. #define BOOT_MODE_OFFSET 0x8
  139. #define RESET_REASON_OFFSET 0x9
  140. #define CH_FLAGS_OFFSET 0xA
  141. #define CH_FLAGS_CHSETTINGS (0x1 << 0)
  142. #define CH_FLAGS_CHRAM (0x1 << 1)
  143. #define CH_FLAGS_CHFLASH (0x1 << 2)
  144. #define CH_FLAGS_CHMMCSD (0x1 << 3)
  145. #ifndef __ASSEMBLY__
  146. struct omap_boot_parameters {
  147. char *boot_message;
  148. unsigned int mem_boot_descriptor;
  149. unsigned char omap_bootdevice;
  150. unsigned char reset_reason;
  151. unsigned char ch_flags;
  152. };
  153. #endif
  154. #endif