clocks.h 8.3 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Aneesh V <aneesh@ti.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #ifndef _CLOCKS_OMAP4_H_
  26. #define _CLOCKS_OMAP4_H_
  27. #include <common.h>
  28. #include <asm/omap_common.h>
  29. /*
  30. * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
  31. * loop, allow for a minimum of 2 ms wait (in reality the wait will be
  32. * much more than that)
  33. */
  34. #define LDELAY 1000000
  35. #define CM_CLKMODE_DPLL_CORE 0x4A004120
  36. #define CM_CLKMODE_DPLL_PER 0x4A008140
  37. #define CM_CLKMODE_DPLL_MPU 0x4A004160
  38. #define CM_CLKSEL_CORE 0x4A004100
  39. /* DPLL register offsets */
  40. #define CM_CLKMODE_DPLL 0
  41. #define CM_IDLEST_DPLL 0x4
  42. #define CM_AUTOIDLE_DPLL 0x8
  43. #define CM_CLKSEL_DPLL 0xC
  44. #define CM_DIV_M2_DPLL 0x10
  45. #define CM_DIV_M3_DPLL 0x14
  46. #define CM_DIV_M4_DPLL 0x18
  47. #define CM_DIV_M5_DPLL 0x1C
  48. #define CM_DIV_M6_DPLL 0x20
  49. #define CM_DIV_M7_DPLL 0x24
  50. #define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
  51. /* CM_DLL_CTRL */
  52. #define CM_DLL_CTRL_OVERRIDE_SHIFT 0
  53. #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
  54. #define CM_DLL_CTRL_NO_OVERRIDE 0
  55. /* CM_CLKMODE_DPLL */
  56. #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
  57. #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
  58. #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
  59. #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
  60. #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
  61. #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
  62. #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
  63. #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
  64. #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
  65. #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
  66. #define CM_CLKMODE_DPLL_EN_SHIFT 0
  67. #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
  68. #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
  69. #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
  70. #define DPLL_EN_STOP 1
  71. #define DPLL_EN_MN_BYPASS 4
  72. #define DPLL_EN_LOW_POWER_BYPASS 5
  73. #define DPLL_EN_FAST_RELOCK_BYPASS 6
  74. #define DPLL_EN_LOCK 7
  75. /* CM_IDLEST_DPLL fields */
  76. #define ST_DPLL_CLK_MASK 1
  77. /* CM_CLKSEL_DPLL */
  78. #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
  79. #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
  80. #define CM_CLKSEL_DPLL_M_SHIFT 8
  81. #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
  82. #define CM_CLKSEL_DPLL_N_SHIFT 0
  83. #define CM_CLKSEL_DPLL_N_MASK 0x7F
  84. #define CM_CLKSEL_DCC_EN_SHIFT 22
  85. #define CM_CLKSEL_DCC_EN_MASK (1 << 22)
  86. #define OMAP4_DPLL_MAX_N 127
  87. /* CM_SYS_CLKSEL */
  88. #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
  89. /* CM_CLKSEL_CORE */
  90. #define CLKSEL_CORE_SHIFT 0
  91. #define CLKSEL_L3_SHIFT 4
  92. #define CLKSEL_L4_SHIFT 8
  93. #define CLKSEL_CORE_X2_DIV_1 0
  94. #define CLKSEL_L3_CORE_DIV_2 1
  95. #define CLKSEL_L4_L3_DIV_2 1
  96. /* CM_ABE_PLL_REF_CLKSEL */
  97. #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
  98. #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
  99. #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
  100. #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
  101. /* CM_BYPCLK_DPLL_IVA */
  102. #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
  103. #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
  104. #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
  105. /* CM_SHADOW_FREQ_CONFIG1 */
  106. #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
  107. #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
  108. #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
  109. #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
  110. #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
  111. #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
  112. #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
  113. /*CM_<clock_domain>__CLKCTRL */
  114. #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
  115. #define CD_CLKCTRL_CLKTRCTRL_MASK 3
  116. #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
  117. #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
  118. #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
  119. #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
  120. /* CM_<clock_domain>_<module>_CLKCTRL */
  121. #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
  122. #define MODULE_CLKCTRL_MODULEMODE_MASK 3
  123. #define MODULE_CLKCTRL_IDLEST_SHIFT 16
  124. #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
  125. #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
  126. #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
  127. #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
  128. #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
  129. #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
  130. #define MODULE_CLKCTRL_IDLEST_IDLE 2
  131. #define MODULE_CLKCTRL_IDLEST_DISABLED 3
  132. /* CM_L4PER_GPIO4_CLKCTRL */
  133. #define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
  134. /* CM_L3INIT_HSMMCn_CLKCTRL */
  135. #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
  136. /* CM_WKUP_GPTIMER1_CLKCTRL */
  137. #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
  138. /* CM_CAM_ISS_CLKCTRL */
  139. #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
  140. /* CM_DSS_DSS_CLKCTRL */
  141. #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
  142. /* CM_L3INIT_USBPHY_CLKCTRL */
  143. #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
  144. /* CM_MPU_MPU_CLKCTRL */
  145. #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
  146. #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
  147. #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
  148. #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
  149. /* Clock frequencies */
  150. #define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
  151. #define OMAP_SYS_CLK_IND_38_4_MHZ 6
  152. #define OMAP_32K_CLK_FREQ 32768
  153. /* PRM_VC_VAL_BYPASS */
  154. #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
  155. /* SMPS */
  156. #define SMPS_I2C_SLAVE_ADDR 0x12
  157. #define SMPS_REG_ADDR_VCORE1 0x55
  158. #define SMPS_REG_ADDR_VCORE2 0x5B
  159. #define SMPS_REG_ADDR_VCORE3 0x61
  160. #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700
  161. #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
  162. /* TPS */
  163. #define TPS62361_I2C_SLAVE_ADDR 0x60
  164. #define TPS62361_REG_ADDR_SET0 0x0
  165. #define TPS62361_REG_ADDR_SET1 0x1
  166. #define TPS62361_REG_ADDR_SET2 0x2
  167. #define TPS62361_REG_ADDR_SET3 0x3
  168. #define TPS62361_REG_ADDR_CTRL 0x4
  169. #define TPS62361_REG_ADDR_TEMP 0x5
  170. #define TPS62361_REG_ADDR_RMP_CTRL 0x6
  171. #define TPS62361_REG_ADDR_CHIP_ID 0x8
  172. #define TPS62361_REG_ADDR_CHIP_ID_2 0x9
  173. #define TPS62361_BASE_VOLT_MV 500
  174. #define TPS62361_VSEL0_GPIO 7
  175. /* AUXCLKx reg fields */
  176. #define AUXCLK_ENABLE_MASK (1 << 8)
  177. #define AUXCLK_SRCSELECT_SHIFT 1
  178. #define AUXCLK_SRCSELECT_MASK (3 << 1)
  179. #define AUXCLK_CLKDIV_SHIFT 16
  180. #define AUXCLK_CLKDIV_MASK (0xF << 16)
  181. #define AUXCLK_SRCSELECT_SYS_CLK 0
  182. #define AUXCLK_SRCSELECT_CORE_DPLL 1
  183. #define AUXCLK_SRCSELECT_PER_DPLL 2
  184. #define AUXCLK_SRCSELECT_ALTERNATE 3
  185. #define AUXCLK_CLKDIV_2 1
  186. #define AUXCLK_CLKDIV_16 0xF
  187. /* ALTCLKSRC */
  188. #define ALTCLKSRC_MODE_MASK 3
  189. #define ALTCLKSRC_ENABLE_INT_MASK 4
  190. #define ALTCLKSRC_ENABLE_EXT_MASK 8
  191. #define ALTCLKSRC_MODE_ACTIVE 1
  192. /* Defines for DPLL setup */
  193. #define DPLL_LOCKED_FREQ_TOLERANCE_0 0
  194. #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
  195. #define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
  196. #define DPLL_NO_LOCK 0
  197. #define DPLL_LOCK 1
  198. struct omap4_scrm_regs {
  199. u32 revision; /* 0x0000 */
  200. u32 pad00[63];
  201. u32 clksetuptime; /* 0x0100 */
  202. u32 pmicsetuptime; /* 0x0104 */
  203. u32 pad01[2];
  204. u32 altclksrc; /* 0x0110 */
  205. u32 pad02[2];
  206. u32 c2cclkm; /* 0x011c */
  207. u32 pad03[56];
  208. u32 extclkreq; /* 0x0200 */
  209. u32 accclkreq; /* 0x0204 */
  210. u32 pwrreq; /* 0x0208 */
  211. u32 pad04[1];
  212. u32 auxclkreq0; /* 0x0210 */
  213. u32 auxclkreq1; /* 0x0214 */
  214. u32 auxclkreq2; /* 0x0218 */
  215. u32 auxclkreq3; /* 0x021c */
  216. u32 auxclkreq4; /* 0x0220 */
  217. u32 auxclkreq5; /* 0x0224 */
  218. u32 pad05[3];
  219. u32 c2cclkreq; /* 0x0234 */
  220. u32 pad06[54];
  221. u32 auxclk0; /* 0x0310 */
  222. u32 auxclk1; /* 0x0314 */
  223. u32 auxclk2; /* 0x0318 */
  224. u32 auxclk3; /* 0x031c */
  225. u32 auxclk4; /* 0x0320 */
  226. u32 auxclk5; /* 0x0324 */
  227. u32 pad07[54];
  228. u32 rsttime_reg; /* 0x0400 */
  229. u32 pad08[6];
  230. u32 c2crstctrl; /* 0x041c */
  231. u32 extpwronrstctrl; /* 0x0420 */
  232. u32 pad09[59];
  233. u32 extwarmrstst_reg; /* 0x0510 */
  234. u32 apewarmrstst_reg; /* 0x0514 */
  235. u32 pad10[1];
  236. u32 c2cwarmrstst_reg; /* 0x051C */
  237. };
  238. #endif /* _CLOCKS_OMAP4_H_ */