dss.h 6.6 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Texas Instruments, <www.ti.com>
  4. * Syed Mohammed Khasim <khasim@ti.com>
  5. *
  6. * Referred to Linux Kernel DSS driver files for OMAP3 by
  7. * Tomi Valkeinen from drivers/video/omap2/dss/
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation's version 2 and any
  15. * later version the License.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #ifndef DSS_H
  28. #define DSS_H
  29. /* DSS Base Registers */
  30. #define OMAP3_DSS_BASE 0x48050000
  31. #define OMAP3_DISPC_BASE 0x48050400
  32. #define OMAP3_VENC_BASE 0x48050C00
  33. /* DSS Registers */
  34. struct dss_regs {
  35. u32 revision; /* 0x00 */
  36. u8 res1[12]; /* 0x04 */
  37. u32 sysconfig; /* 0x10 */
  38. u32 sysstatus; /* 0x14 */
  39. u32 irqstatus; /* 0x18 */
  40. u8 res2[36]; /* 0x1C */
  41. u32 control; /* 0x40 */
  42. u32 sdi_control; /* 0x44 */
  43. u32 pll_control; /* 0x48 */
  44. };
  45. /* DISPC Registers */
  46. struct dispc_regs {
  47. u32 revision; /* 0x00 */
  48. u8 res1[12]; /* 0x04 */
  49. u32 sysconfig; /* 0x10 */
  50. u32 sysstatus; /* 0x14 */
  51. u32 irqstatus; /* 0x18 */
  52. u32 irqenable; /* 0x1C */
  53. u8 res2[32]; /* 0x20 */
  54. u32 control; /* 0x40 */
  55. u32 config; /* 0x44 */
  56. u32 reserve_2; /* 0x48 */
  57. u32 default_color0; /* 0x4C */
  58. u32 default_color1; /* 0x50 */
  59. u32 trans_color0; /* 0x54 */
  60. u32 trans_color1; /* 0x58 */
  61. u32 line_status; /* 0x5C */
  62. u32 line_number; /* 0x60 */
  63. u32 timing_h; /* 0x64 */
  64. u32 timing_v; /* 0x68 */
  65. u32 pol_freq; /* 0x6C */
  66. u32 divisor; /* 0x70 */
  67. u32 global_alpha; /* 0x74 */
  68. u32 size_dig; /* 0x78 */
  69. u32 size_lcd; /* 0x7C */
  70. u32 gfx_ba0; /* 0x80 */
  71. u32 gfx_ba1; /* 0x84 */
  72. u32 gfx_position; /* 0x88 */
  73. u32 gfx_size; /* 0x8C */
  74. u8 unused[16]; /* 0x90 */
  75. u32 gfx_attributes; /* 0xA0 */
  76. u32 gfx_fifo_threshold; /* 0xA4 */
  77. u32 gfx_fifo_size_status; /* 0xA8 */
  78. u32 gfx_row_inc; /* 0xAC */
  79. u32 gfx_pixel_inc; /* 0xB0 */
  80. u32 gfx_window_skip; /* 0xB4 */
  81. u32 gfx_table_ba; /* 0xB8 */
  82. };
  83. /* VENC Registers */
  84. struct venc_regs {
  85. u32 rev_id; /* 0x00 */
  86. u32 status; /* 0x04 */
  87. u32 f_control; /* 0x08 */
  88. u32 reserve_1; /* 0x0C */
  89. u32 vidout_ctrl; /* 0x10 */
  90. u32 sync_ctrl; /* 0x14 */
  91. u32 reserve_2; /* 0x18 */
  92. u32 llen; /* 0x1C */
  93. u32 flens; /* 0x20 */
  94. u32 hfltr_ctrl; /* 0x24 */
  95. u32 cc_carr_wss_carr; /* 0x28 */
  96. u32 c_phase; /* 0x2C */
  97. u32 gain_u; /* 0x30 */
  98. u32 gain_v; /* 0x34 */
  99. u32 gain_y; /* 0x38 */
  100. u32 black_level; /* 0x3C */
  101. u32 blank_level; /* 0x40 */
  102. u32 x_color; /* 0x44 */
  103. u32 m_control; /* 0x48 */
  104. u32 bstamp_wss_data; /* 0x4C */
  105. u32 s_carr; /* 0x50 */
  106. u32 line21; /* 0x54 */
  107. u32 ln_sel; /* 0x58 */
  108. u32 l21__wc_ctl; /* 0x5C */
  109. u32 htrigger_vtrigger; /* 0x60 */
  110. u32 savid__eavid; /* 0x64 */
  111. u32 flen__fal; /* 0x68 */
  112. u32 lal__phase_reset; /* 0x6C */
  113. u32 hs_int_start_stop_x; /* 0x70 */
  114. u32 hs_ext_start_stop_x; /* 0x74 */
  115. u32 vs_int_start_x; /* 0x78 */
  116. u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */
  117. u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */
  118. u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */
  119. u32 vs_ext_stop_y; /* 0x88 */
  120. u32 reserve_3; /* 0x8C */
  121. u32 avid_start_stop_x; /* 0x90 */
  122. u32 avid_start_stop_y; /* 0x94 */
  123. u32 reserve_4; /* 0x98 */
  124. u32 reserve_5; /* 0x9C */
  125. u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */
  126. u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */
  127. u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */
  128. u32 reserve_6; /* 0xAC */
  129. u32 tvdetgp_int_start_stop_x; /* 0xB0 */
  130. u32 tvdetgp_int_start_stop_y; /* 0xB4 */
  131. u32 gen_ctrl; /* 0xB8 */
  132. u32 reserve_7; /* 0xBC */
  133. u32 reserve_8; /* 0xC0 */
  134. u32 output_control; /* 0xC4 */
  135. u32 dac_b__dac_c; /* 0xC8 */
  136. u32 height_width; /* 0xCC */
  137. };
  138. /* Few Register Offsets */
  139. #define TFTSTN_SHIFT 3
  140. #define DATALINES_SHIFT 8
  141. #define GFX_ENABLE 1
  142. #define GFX_FORMAT_SHIFT 1
  143. #define LOADMODE_SHIFT 1
  144. #define DSS_SOFTRESET (1 << 1)
  145. #define DSS_RESETDONE 1
  146. /* Enabling Display controller */
  147. #define LCD_ENABLE 1
  148. #define DIG_ENABLE (1 << 1)
  149. #define GO_LCD (1 << 5)
  150. #define GO_DIG (1 << 6)
  151. #define GP_OUT0 (1 << 15)
  152. #define GP_OUT1 (1 << 16)
  153. /* Configure VENC DSS Params */
  154. #define VENC_CLK_ENABLE (1 << 3)
  155. #define DAC_DEMEN (1 << 4)
  156. #define DAC_POWERDN (1 << 5)
  157. #define VENC_OUT_SEL (1 << 6)
  158. #define DIG_LPP_SHIFT 16
  159. /* LCD display type */
  160. #define PASSIVE_DISPLAY 0
  161. #define ACTIVE_DISPLAY 1
  162. /* TFTDATALINES */
  163. #define LCD_INTERFACE_12_BIT 0
  164. #define LCD_INTERFACE_16_BIT 1
  165. #define LCD_INTERFACE_18_BIT 2
  166. #define LCD_INTERFACE_24_BIT 3
  167. /* Polarity */
  168. #define DSS_IVS (1 << 12)
  169. #define DSS_IHS (1 << 13)
  170. #define DSS_IPC (1 << 14)
  171. #define DSS_IEO (1 << 15)
  172. /* GFX format */
  173. #define GFXFORMAT_BITMAP1 (0x0 << 1)
  174. #define GFXFORMAT_BITMAP2 (0x1 << 1)
  175. #define GFXFORMAT_BITMAP4 (0x2 << 1)
  176. #define GFXFORMAT_BITMAP8 (0x3 << 1)
  177. #define GFXFORMAT_RGB12 (0x4 << 1)
  178. #define GFXFORMAT_ARGB16 (0x5 << 1)
  179. #define GFXFORMAT_RGB16 (0x6 << 1)
  180. #define GFXFORMAT_RGB24_UNPACKED (0x8 << 1)
  181. #define GFXFORMAT_RGB24_PACKED (0x9 << 1)
  182. #define GFXFORMAT_ARGB32 (0xC << 1)
  183. #define GFXFORMAT_RGBA32 (0xD << 1)
  184. #define GFXFORMAT_RGBx32 (0xE << 1)
  185. /* Panel Configuration */
  186. struct panel_config {
  187. u32 timing_h;
  188. u32 timing_v;
  189. u32 pol_freq;
  190. u32 divisor;
  191. u32 lcd_size;
  192. u32 panel_type;
  193. u32 data_lines;
  194. u32 load_mode;
  195. u32 panel_color;
  196. u32 gfx_format;
  197. void *frame_buffer;
  198. };
  199. #define DSS_HBP(bp) (((bp) - 1) << 20)
  200. #define DSS_HFP(fp) (((fp) - 1) << 8)
  201. #define DSS_HSW(sw) ((sw) - 1)
  202. #define DSS_VBP(bp) ((bp) << 20)
  203. #define DSS_VFP(fp) ((fp) << 8)
  204. #define DSS_VSW(sw) ((sw) - 1)
  205. #define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
  206. #define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
  207. #define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1))
  208. /* Generic DSS Functions */
  209. void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
  210. u32 height, u32 width);
  211. void omap3_dss_panel_config(const struct panel_config *panel_cfg);
  212. void omap3_dss_enable(void);
  213. #endif /* DSS_H */