dma.h 4.6 KB

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  1. /*
  2. * Freescale i.MX28 APBH DMA
  3. *
  4. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  5. * on behalf of DENX Software Engineering GmbH
  6. *
  7. * Based on code from LTIB:
  8. * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. *
  24. */
  25. #ifndef __DMA_H__
  26. #define __DMA_H__
  27. #include <linux/list.h>
  28. #include <linux/compiler.h>
  29. #ifndef CONFIG_ARCH_DMA_PIO_WORDS
  30. #define DMA_PIO_WORDS 15
  31. #else
  32. #define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
  33. #endif
  34. #define MXS_DMA_ALIGNMENT 32
  35. /*
  36. * MXS DMA channels
  37. */
  38. #if defined(CONFIG_MX23)
  39. enum {
  40. MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
  41. MXS_DMA_CHANNEL_AHB_APBH_SSP0,
  42. MXS_DMA_CHANNEL_AHB_APBH_SSP1,
  43. MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
  44. MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
  45. MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
  46. MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
  47. MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
  48. MXS_MAX_DMA_CHANNELS,
  49. };
  50. #elif defined(CONFIG_MX28)
  51. enum {
  52. MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
  53. MXS_DMA_CHANNEL_AHB_APBH_SSP1,
  54. MXS_DMA_CHANNEL_AHB_APBH_SSP2,
  55. MXS_DMA_CHANNEL_AHB_APBH_SSP3,
  56. MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
  57. MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
  58. MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
  59. MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
  60. MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
  61. MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
  62. MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
  63. MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
  64. MXS_DMA_CHANNEL_AHB_APBH_HSADC,
  65. MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
  66. MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
  67. MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
  68. MXS_MAX_DMA_CHANNELS,
  69. };
  70. #endif
  71. /*
  72. * MXS DMA hardware command.
  73. *
  74. * This structure describes the in-memory layout of an entire DMA command,
  75. * including space for the maximum number of PIO accesses. See the appropriate
  76. * reference manual for a detailed description of what these fields mean to the
  77. * DMA hardware.
  78. */
  79. #define MXS_DMA_DESC_COMMAND_MASK 0x3
  80. #define MXS_DMA_DESC_COMMAND_OFFSET 0
  81. #define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
  82. #define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
  83. #define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
  84. #define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
  85. #define MXS_DMA_DESC_CHAIN (1 << 2)
  86. #define MXS_DMA_DESC_IRQ (1 << 3)
  87. #define MXS_DMA_DESC_NAND_LOCK (1 << 4)
  88. #define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
  89. #define MXS_DMA_DESC_DEC_SEM (1 << 6)
  90. #define MXS_DMA_DESC_WAIT4END (1 << 7)
  91. #define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
  92. #define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
  93. #define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
  94. #define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
  95. #define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
  96. #define MXS_DMA_DESC_BYTES_OFFSET 16
  97. struct mxs_dma_cmd {
  98. unsigned long next;
  99. unsigned long data;
  100. union {
  101. dma_addr_t address;
  102. unsigned long alternate;
  103. };
  104. unsigned long pio_words[DMA_PIO_WORDS];
  105. };
  106. /*
  107. * MXS DMA command descriptor.
  108. *
  109. * This structure incorporates an MXS DMA hardware command structure, along
  110. * with metadata.
  111. */
  112. #define MXS_DMA_DESC_FIRST (1 << 0)
  113. #define MXS_DMA_DESC_LAST (1 << 1)
  114. #define MXS_DMA_DESC_READY (1 << 31)
  115. struct mxs_dma_desc {
  116. struct mxs_dma_cmd cmd;
  117. unsigned int flags;
  118. dma_addr_t address;
  119. void *buffer;
  120. struct list_head node;
  121. } __aligned(MXS_DMA_ALIGNMENT);
  122. /**
  123. * MXS DMA channel
  124. *
  125. * This structure represents a single DMA channel. The MXS platform code
  126. * maintains an array of these structures to represent every DMA channel in the
  127. * system (see mxs_dma_channels).
  128. */
  129. #define MXS_DMA_FLAGS_IDLE 0
  130. #define MXS_DMA_FLAGS_BUSY (1 << 0)
  131. #define MXS_DMA_FLAGS_FREE 0
  132. #define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
  133. #define MXS_DMA_FLAGS_VALID (1 << 31)
  134. struct mxs_dma_chan {
  135. const char *name;
  136. unsigned long dev;
  137. struct mxs_dma_device *dma;
  138. unsigned int flags;
  139. unsigned int active_num;
  140. unsigned int pending_num;
  141. struct list_head active;
  142. struct list_head done;
  143. };
  144. struct mxs_dma_desc *mxs_dma_desc_alloc(void);
  145. void mxs_dma_desc_free(struct mxs_dma_desc *);
  146. int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
  147. int mxs_dma_go(int chan);
  148. void mxs_dma_init(void);
  149. int mxs_dma_init_channel(int chan);
  150. int mxs_dma_release(int chan);
  151. #endif /* __DMA_H__ */