mxc_hdmi.h 35 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064
  1. /*
  2. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  3. */
  4. /*
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, write to the Free Software Foundation, Inc.,
  17. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  18. */
  19. #ifndef __MXC_HDMI_H__
  20. #define __MXC_HDMI_H__
  21. /*
  22. * Hdmi controller registers
  23. */
  24. struct hdmi_regs {
  25. /*Identification Registers */
  26. u8 design_id; /* 0x000 */
  27. u8 revision_id; /* 0x001 */
  28. u8 product_id0; /* 0x002 */
  29. u8 product_id1; /* 0x003 */
  30. u8 config0_id; /* 0x004 */
  31. u8 config1_id; /* 0x005 */
  32. u8 config2_id; /* 0x006 */
  33. u8 config3_id; /* 0x007 */
  34. u8 reserved1[0xf8];
  35. /* Interrupt Registers */
  36. u8 ih_fc_stat0; /* 0x100 */
  37. u8 ih_fc_stat1; /* 0x101 */
  38. u8 ih_fc_stat2; /* 0x102 */
  39. u8 ih_as_stat0; /* 0x103 */
  40. u8 ih_phy_stat0; /* 0x104 */
  41. u8 ih_i2cm_stat0; /* 0x105 */
  42. u8 ih_cec_stat0; /* 0x106 */
  43. u8 ih_vp_stat0; /* 0x107 */
  44. u8 ih_i2cmphy_stat0; /* 0x108 */
  45. u8 ih_ahbdmaaud_stat0; /* 0x109 */
  46. u8 reserved2[0x76];
  47. u8 ih_mute_fc_stat0; /* 0x180 */
  48. u8 ih_mute_fc_stat1; /* 0x181 */
  49. u8 ih_mute_fc_stat2; /* 0x182 */
  50. u8 ih_mute_as_stat0; /* 0x183 */
  51. u8 ih_mute_phy_stat0; /* 0x184 */
  52. u8 ih_mute_i2cm_stat0; /* 0x185 */
  53. u8 ih_mute_cec_stat0; /* 0x186 */
  54. u8 ih_mute_vp_stat0; /* 0x187 */
  55. u8 ih_mute_i2cmphy_stat0; /* 0x188 */
  56. u8 ih_mute_ahbdmaaud_stat0; /* 0x189 */
  57. u8 reserved3[0x75];
  58. u8 ih_mute; /* 0x1ff */
  59. /* Video Sample Registers */
  60. u8 tx_invid0; /* 0x200 */
  61. u8 tx_instuffing; /* 0x201 */
  62. u8 tx_gydata0; /* 0x202 */
  63. u8 tx_gydata1; /* 0x203 */
  64. u8 tx_rcrdata0; /* 0x204 */
  65. u8 tx_rcrdata1; /* 0x205 */
  66. u8 tx_bcbdata0; /* 0x206 */
  67. u8 tx_bcbdata1; /* 0x207 */
  68. u8 reserved4[0x5f8];
  69. /* Video Packetizer Registers */
  70. u8 vp_status; /* 0x800 */
  71. u8 vp_pr_cd; /* 0x801 */
  72. u8 vp_stuff; /* 0x802 */
  73. u8 vp_remap; /* 0x803 */
  74. u8 vp_conf; /* 0x804 */
  75. u8 vp_stat; /* 0x805 */
  76. u8 vp_int; /* 0x806 */
  77. u8 vp_mask; /* 0x807 */
  78. u8 vp_pol; /* 0x808 */
  79. u8 reserved5[0x7f7];
  80. /* Frame Composer Registers */
  81. u8 fc_invidconf; /* 0x1000 */
  82. u8 fc_inhactv0; /* 0x1001 */
  83. u8 fc_inhactv1; /* 0x1002 */
  84. u8 fc_inhblank0; /* 0x1003 */
  85. u8 fc_inhblank1; /* 0x1004 */
  86. u8 fc_invactv0; /* 0x1005 */
  87. u8 fc_invactv1; /* 0x1006 */
  88. u8 fc_invblank; /* 0x1007 */
  89. u8 fc_hsyncindelay0; /* 0x1008 */
  90. u8 fc_hsyncindelay1; /* 0x1009 */
  91. u8 fc_hsyncinwidth0; /* 0x100a */
  92. u8 fc_hsyncinwidth1; /* 0x100b */
  93. u8 fc_vsyncindelay; /* 0x100c */
  94. u8 fc_vsyncinwidth; /* 0x100d */
  95. u8 fc_infreq0; /* 0x100e */
  96. u8 fc_infreq1; /* 0x100f */
  97. u8 fc_infreq2; /* 0x1010 */
  98. u8 fc_ctrldur; /* 0x1011 */
  99. u8 fc_exctrldur; /* 0x1012 */
  100. u8 fc_exctrlspac; /* 0x1013 */
  101. u8 fc_ch0pream; /* 0x1014 */
  102. u8 fc_ch1pream; /* 0x1015 */
  103. u8 fc_ch2pream; /* 0x1016 */
  104. u8 fc_aviconf3; /* 0x1017 */
  105. u8 fc_gcp; /* 0x1018 */
  106. u8 fc_aviconf0; /* 0x1019 */
  107. u8 fc_aviconf1; /* 0x101a */
  108. u8 fc_aviconf2; /* 0x101b */
  109. u8 fc_avivid; /* 0x101c */
  110. u8 fc_avietb0; /* 0x101d */
  111. u8 fc_avietb1; /* 0x101e */
  112. u8 fc_avisbb0; /* 0x101f */
  113. u8 fc_avisbb1; /* 0x1020 */
  114. u8 fc_avielb0; /* 0x1021 */
  115. u8 fc_avielb1; /* 0x1022 */
  116. u8 fc_avisrb0; /* 0x1023 */
  117. u8 fc_avisrb1; /* 0x1024 */
  118. u8 fc_audiconf0; /* 0x1025 */
  119. u8 fc_audiconf1; /* 0x1026 */
  120. u8 fc_audiconf2; /* 0x1027 */
  121. u8 fc_audiconf3; /* 0x1028 */
  122. u8 fc_vsdieeeid0; /* 0x1029 */
  123. u8 fc_vsdsize; /* 0x102a */
  124. u8 reserved6[5];
  125. u8 fc_vsdieeeid1; /* 0x1030 */
  126. u8 fc_vsdieeeid2; /* 0x1031 */
  127. u8 fc_vsdpayload0; /* 0x1032 */
  128. u8 fc_vsdpayload1; /* 0x1033 */
  129. u8 fc_vsdpayload2; /* 0x1034 */
  130. u8 fc_vsdpayload3; /* 0x1035 */
  131. u8 fc_vsdpayload4; /* 0x1036 */
  132. u8 fc_vsdpayload5; /* 0x1037 */
  133. u8 fc_vsdpayload6; /* 0x1038 */
  134. u8 fc_vsdpayload7; /* 0x1039 */
  135. u8 fc_vsdpayload8; /* 0x103a */
  136. u8 fc_vsdpayload9; /* 0x103b */
  137. u8 fc_vsdpayload10; /* 0x103c */
  138. u8 fc_vsdpayload11; /* 0x103d */
  139. u8 fc_vsdpayload12; /* 0x103e */
  140. u8 fc_vsdpayload13; /* 0x103f */
  141. u8 fc_vsdpayload14; /* 0x1040 */
  142. u8 fc_vsdpayload15; /* 0x1041 */
  143. u8 fc_vsdpayload16; /* 0x1042 */
  144. u8 fc_vsdpayload17; /* 0x1043 */
  145. u8 fc_vsdpayload18; /* 0x1044 */
  146. u8 fc_vsdpayload19; /* 0x1045 */
  147. u8 fc_vsdpayload20; /* 0x1046 */
  148. u8 fc_vsdpayload21; /* 0x1047 */
  149. u8 fc_vsdpayload22; /* 0x1048 */
  150. u8 fc_vsdpayload23; /* 0x1049 */
  151. u8 fc_spdvendorname0; /* 0x104a */
  152. u8 fc_spdvendorname1; /* 0x104b */
  153. u8 fc_spdvendorname2; /* 0x104c */
  154. u8 fc_spdvendorname3; /* 0x104d */
  155. u8 fc_spdvendorname4; /* 0x104e */
  156. u8 fc_spdvendorname5; /* 0x104f */
  157. u8 fc_spdvendorname6; /* 0x1050 */
  158. u8 fc_spdvendorname7; /* 0x1051 */
  159. u8 fc_sdpproductname0; /* 0x1052 */
  160. u8 fc_sdpproductname1; /* 0x1053 */
  161. u8 fc_sdpproductname2; /* 0x1054 */
  162. u8 fc_sdpproductname3; /* 0x1055 */
  163. u8 fc_sdpproductname4; /* 0x1056 */
  164. u8 fc_sdpproductname5; /* 0x1057 */
  165. u8 fc_sdpproductname6; /* 0x1058 */
  166. u8 fc_sdpproductname7; /* 0x1059 */
  167. u8 fc_sdpproductname8; /* 0x105a */
  168. u8 fc_sdpproductname9; /* 0x105b */
  169. u8 fc_sdpproductname10; /* 0x105c */
  170. u8 fc_sdpproductname11; /* 0x105d */
  171. u8 fc_sdpproductname12; /* 0x105e */
  172. u8 fc_sdpproductname13; /* 0x105f */
  173. u8 fc_sdpproductname14; /* 0x1060 */
  174. u8 fc_spdproductname15; /* 0x1061 */
  175. u8 fc_spddeviceinf; /* 0x1062 */
  176. u8 fc_audsconf; /* 0x1063 */
  177. u8 fc_audsstat; /* 0x1064 */
  178. u8 reserved7[0xb];
  179. u8 fc_datach0fill; /* 0x1070 */
  180. u8 fc_datach1fill; /* 0x1071 */
  181. u8 fc_datach2fill; /* 0x1072 */
  182. u8 fc_ctrlqhigh; /* 0x1073 */
  183. u8 fc_ctrlqlow; /* 0x1074 */
  184. u8 fc_acp0; /* 0x1075 */
  185. u8 fc_acp28; /* 0x1076 */
  186. u8 fc_acp27; /* 0x1077 */
  187. u8 fc_acp26; /* 0x1078 */
  188. u8 fc_acp25; /* 0x1079 */
  189. u8 fc_acp24; /* 0x107a */
  190. u8 fc_acp23; /* 0x107b */
  191. u8 fc_acp22; /* 0x107c */
  192. u8 fc_acp21; /* 0x107d */
  193. u8 fc_acp20; /* 0x107e */
  194. u8 fc_acp19; /* 0x107f */
  195. u8 fc_acp18; /* 0x1080 */
  196. u8 fc_acp17; /* 0x1081 */
  197. u8 fc_acp16; /* 0x1082 */
  198. u8 fc_acp15; /* 0x1083 */
  199. u8 fc_acp14; /* 0x1084 */
  200. u8 fc_acp13; /* 0x1085 */
  201. u8 fc_acp12; /* 0x1086 */
  202. u8 fc_acp11; /* 0x1087 */
  203. u8 fc_acp10; /* 0x1088 */
  204. u8 fc_acp9; /* 0x1089 */
  205. u8 fc_acp8; /* 0x108a */
  206. u8 fc_acp7; /* 0x108b */
  207. u8 fc_acp6; /* 0x108c */
  208. u8 fc_acp5; /* 0x108d */
  209. u8 fc_acp4; /* 0x108e */
  210. u8 fc_acp3; /* 0x108f */
  211. u8 fc_acp2; /* 0x1090 */
  212. u8 fc_acp1; /* 0x1091 */
  213. u8 fc_iscr1_0; /* 0x1092 */
  214. u8 fc_iscr1_16; /* 0x1093 */
  215. u8 fc_iscr1_15; /* 0x1094 */
  216. u8 fc_iscr1_14; /* 0x1095 */
  217. u8 fc_iscr1_13; /* 0x1096 */
  218. u8 fc_iscr1_12; /* 0x1097 */
  219. u8 fc_iscr1_11; /* 0x1098 */
  220. u8 fc_iscr1_10; /* 0x1099 */
  221. u8 fc_iscr1_9; /* 0x109a */
  222. u8 fc_iscr1_8; /* 0x109b */
  223. u8 fc_iscr1_7; /* 0x109c */
  224. u8 fc_iscr1_6; /* 0x109d */
  225. u8 fc_iscr1_5; /* 0x109e */
  226. u8 fc_iscr1_4; /* 0x109f */
  227. u8 fc_iscr1_3; /* 0x10a0 */
  228. u8 fc_iscr1_2; /* 0x10a1 */
  229. u8 fc_iscr1_1; /* 0x10a2 */
  230. u8 fc_iscr2_15; /* 0x10a3 */
  231. u8 fc_iscr2_14; /* 0x10a4 */
  232. u8 fc_iscr2_13; /* 0x10a5 */
  233. u8 fc_iscr2_12; /* 0x10a6 */
  234. u8 fc_iscr2_11; /* 0x10a7 */
  235. u8 fc_iscr2_10; /* 0x10a8 */
  236. u8 fc_iscr2_9; /* 0x10a9 */
  237. u8 fc_iscr2_8; /* 0x10aa */
  238. u8 fc_iscr2_7; /* 0x10ab */
  239. u8 fc_iscr2_6; /* 0x10ac */
  240. u8 fc_iscr2_5; /* 0x10ad */
  241. u8 fc_iscr2_4; /* 0x10ae */
  242. u8 fc_iscr2_3; /* 0x10af */
  243. u8 fc_iscr2_2; /* 0x10b0 */
  244. u8 fc_iscr2_1; /* 0x10b1 */
  245. u8 fc_iscr2_0; /* 0x10b2 */
  246. u8 fc_datauto0; /* 0x10b3 */
  247. u8 fc_datauto1; /* 0x10b4 */
  248. u8 fc_datauto2; /* 0x10b5 */
  249. u8 fc_datman; /* 0x10b6 */
  250. u8 fc_datauto3; /* 0x10b7 */
  251. u8 fc_rdrb0; /* 0x10b8 */
  252. u8 fc_rdrb1; /* 0x10b9 */
  253. u8 fc_rdrb2; /* 0x10ba */
  254. u8 fc_rdrb3; /* 0x10bb */
  255. u8 fc_rdrb4; /* 0x10bc */
  256. u8 fc_rdrb5; /* 0x10bd */
  257. u8 fc_rdrb6; /* 0x10be */
  258. u8 fc_rdrb7; /* 0x10bf */
  259. u8 reserved8[0x10];
  260. u8 fc_stat0; /* 0x10d0 */
  261. u8 fc_int0; /* 0x10d1 */
  262. u8 fc_mask0; /* 0x10d2 */
  263. u8 fc_pol0; /* 0x10d3 */
  264. u8 fc_stat1; /* 0x10d4 */
  265. u8 fc_int1; /* 0x10d5 */
  266. u8 fc_mask1; /* 0x10d6 */
  267. u8 fc_pol1; /* 0x10d7 */
  268. u8 fc_stat2; /* 0x10d8 */
  269. u8 fc_int2; /* 0x10d9 */
  270. u8 fc_mask2; /* 0x10da */
  271. u8 fc_pol2; /* 0x10db */
  272. u8 reserved9[0x4];
  273. u8 fc_prconf; /* 0x10e0 */
  274. u8 reserved10[0x1f];
  275. u8 fc_gmd_stat; /* 0x1100 */
  276. u8 fc_gmd_en; /* 0x1101 */
  277. u8 fc_gmd_up; /* 0x1102 */
  278. u8 fc_gmd_conf; /* 0x1103 */
  279. u8 fc_gmd_hb; /* 0x1104 */
  280. u8 fc_gmd_pb0; /* 0x1105 */
  281. u8 fc_gmd_pb1; /* 0x1106 */
  282. u8 fc_gmd_pb2; /* 0x1107 */
  283. u8 fc_gmd_pb3; /* 0x1108 */
  284. u8 fc_gmd_pb4; /* 0x1109 */
  285. u8 fc_gmd_pb5; /* 0x110a */
  286. u8 fc_gmd_pb6; /* 0x110b */
  287. u8 fc_gmd_pb7; /* 0x110c */
  288. u8 fc_gmd_pb8; /* 0x110d */
  289. u8 fc_gmd_pb9; /* 0x110e */
  290. u8 fc_gmd_pb10; /* 0x110f */
  291. u8 fc_gmd_pb11; /* 0x1110 */
  292. u8 fc_gmd_pb12; /* 0x1111 */
  293. u8 fc_gmd_pb13; /* 0x1112 */
  294. u8 fc_gmd_pb14; /* 0x1113 */
  295. u8 fc_gmd_pb15; /* 0x1114 */
  296. u8 fc_gmd_pb16; /* 0x1115 */
  297. u8 fc_gmd_pb17; /* 0x1116 */
  298. u8 fc_gmd_pb18; /* 0x1117 */
  299. u8 fc_gmd_pb19; /* 0x1118 */
  300. u8 fc_gmd_pb20; /* 0x1119 */
  301. u8 fc_gmd_pb21; /* 0x111a */
  302. u8 fc_gmd_pb22; /* 0x111b */
  303. u8 fc_gmd_pb23; /* 0x111c */
  304. u8 fc_gmd_pb24; /* 0x111d */
  305. u8 fc_gmd_pb25; /* 0x111e */
  306. u8 fc_gmd_pb26; /* 0x111f */
  307. u8 fc_gmd_pb27; /* 0x1120 */
  308. u8 reserved11[0xdf];
  309. u8 fc_dbgforce; /* 0x1200 */
  310. u8 fc_dbgaud0ch0; /* 0x1201 */
  311. u8 fc_dbgaud1ch0; /* 0x1202 */
  312. u8 fc_dbgaud2ch0; /* 0x1203 */
  313. u8 fc_dbgaud0ch1; /* 0x1204 */
  314. u8 fc_dbgaud1ch1; /* 0x1205 */
  315. u8 fc_dbgaud2ch1; /* 0x1206 */
  316. u8 fc_dbgaud0ch2; /* 0x1207 */
  317. u8 fc_dbgaud1ch2; /* 0x1208 */
  318. u8 fc_dbgaud2ch2; /* 0x1209 */
  319. u8 fc_dbgaud0ch3; /* 0x120a */
  320. u8 fc_dbgaud1ch3; /* 0x120b */
  321. u8 fc_dbgaud2ch3; /* 0x120c */
  322. u8 fc_dbgaud0ch4; /* 0x120d */
  323. u8 fc_dbgaud1ch4; /* 0x120e */
  324. u8 fc_dbgaud2ch4; /* 0x120f */
  325. u8 fc_dbgaud0ch5; /* 0x1210 */
  326. u8 fc_dbgaud1ch5; /* 0x1211 */
  327. u8 fc_dbgaud2ch5; /* 0x1212 */
  328. u8 fc_dbgaud0ch6; /* 0x1213 */
  329. u8 fc_dbgaud1ch6; /* 0x1214 */
  330. u8 fc_dbgaud2ch6; /* 0x1215 */
  331. u8 fc_dbgaud0ch7; /* 0x1216 */
  332. u8 fc_dbgaud1ch7; /* 0x1217 */
  333. u8 fc_dbgaud2ch7; /* 0x1218 */
  334. u8 fc_dbgtmds0; /* 0x1219 */
  335. u8 fc_dbgtmds1; /* 0x121a */
  336. u8 fc_dbgtmds2; /* 0x121b */
  337. u8 reserved12[0x1de4];
  338. /* Hdmi Source Phy Registers */
  339. u8 phy_conf0; /* 0x3000 */
  340. u8 phy_tst0; /* 0x3001 */
  341. u8 phy_tst1; /* 0x3002 */
  342. u8 phy_tst2; /* 0x3003 */
  343. u8 phy_stat0; /* 0x3004 */
  344. u8 phy_int0; /* 0x3005 */
  345. u8 phy_mask0; /* 0x3006 */
  346. u8 phy_pol0; /* 0x3007 */
  347. u8 reserved13[0x18];
  348. /* Hdmi Master Phy Registers */
  349. u8 phy_i2cm_slave_addr; /* 0x3020 */
  350. u8 phy_i2cm_address_addr; /* 0x3021 */
  351. u8 phy_i2cm_datao_1_addr; /* 0x3022 */
  352. u8 phy_i2cm_datao_0_addr; /* 0x3023 */
  353. u8 phy_i2cm_datai_1_addr; /* 0x3024 */
  354. u8 phy_i2cm_datai_0_addr; /* 0x3025 */
  355. u8 phy_i2cm_operation_addr; /* 0x3026 */
  356. u8 phy_i2cm_int_addr; /* 0x3027 */
  357. u8 phy_i2cm_ctlint_addr; /* 0x3028 */
  358. u8 phy_i2cm_div_addr; /* 0x3029 */
  359. u8 phy_i2cm_softrstz_addr; /* 0x302a */
  360. u8 phy_i2cm_ss_scl_hcnt_1_addr; /* 0x302b */
  361. u8 phy_i2cm_ss_scl_hcnt_0_addr; /* 0x302c */
  362. u8 phy_i2cm_ss_scl_lcnt_1_addr; /* 0x302d */
  363. u8 phy_i2cm_ss_scl_lcnt_0_addr; /* 0x302e */
  364. u8 phy_i2cm_fs_scl_hcnt_1_addr; /* 0x302f */
  365. u8 phy_i2cm_fs_scl_hcnt_0_addr; /* 0x3030 */
  366. u8 phy_i2cm_fs_scl_lcnt_1_addr; /* 0x3031 */
  367. u8 phy_i2cm_fs_scl_lcnt_0_addr; /* 0x3032 */
  368. u8 reserved14[0xcd];
  369. /* Audio Sampler Registers */
  370. u8 aud_conf0; /* 0x3100 */
  371. u8 aud_conf1; /* 0x3101 */
  372. u8 aud_int; /* 0x3102 */
  373. u8 aud_conf2; /* 0x3103 */
  374. u8 reserved15[0xfc];
  375. u8 aud_n1; /* 0x3200 */
  376. u8 aud_n2; /* 0x3201 */
  377. u8 aud_n3; /* 0x3202 */
  378. u8 aud_cts1; /* 0x3203 */
  379. u8 aud_cts2; /* 0x3204 */
  380. u8 aud_cts3; /* 0x3205 */
  381. u8 aud_inputclkfs; /* 0x3206 */
  382. u8 reserved16[0xfb];
  383. u8 aud_spdifint; /* 0x3302 */
  384. u8 reserved17[0xfd];
  385. u8 aud_conf0_hbr; /* 0x3400 */
  386. u8 aud_hbr_status; /* 0x3401 */
  387. u8 aud_hbr_int; /* 0x3402 */
  388. u8 aud_hbr_pol; /* 0x3403 */
  389. u8 aud_hbr_mask; /* 0x3404 */
  390. u8 reserved18[0xfb];
  391. /*
  392. * Generic Parallel Audio Interface Registers
  393. * Not used as GPAUD interface is not enabled in hw
  394. */
  395. u8 gp_conf0; /* 0x3500 */
  396. u8 gp_conf1; /* 0x3501 */
  397. u8 gp_conf2; /* 0x3502 */
  398. u8 gp_stat; /* 0x3503 */
  399. u8 gp_int; /* 0x3504 */
  400. u8 gp_mask; /* 0x3505 */
  401. u8 gp_pol; /* 0x3506 */
  402. u8 reserved19[0xf9];
  403. /* Audio DMA Registers */
  404. u8 ahb_dma_conf0; /* 0x3600 */
  405. u8 ahb_dma_start; /* 0x3601 */
  406. u8 ahb_dma_stop; /* 0x3602 */
  407. u8 ahb_dma_thrsld; /* 0x3603 */
  408. u8 ahb_dma_straddr0; /* 0x3604 */
  409. u8 ahb_dma_straddr1; /* 0x3605 */
  410. u8 ahb_dma_straddr2; /* 0x3606 */
  411. u8 ahb_dma_straddr3; /* 0x3607 */
  412. u8 ahb_dma_stpaddr0; /* 0x3608 */
  413. u8 ahb_dma_stpaddr1; /* 0x3609 */
  414. u8 ahb_dma_stpaddr2; /* 0x360a */
  415. u8 ahb_dma_stpaddr3; /* 0x360b */
  416. u8 ahb_dma_bstaddr0; /* 0x360c */
  417. u8 ahb_dma_bstaddr1; /* 0x360d */
  418. u8 ahb_dma_bstaddr2; /* 0x360e */
  419. u8 ahb_dma_bstaddr3; /* 0x360f */
  420. u8 ahb_dma_mblength0; /* 0x3610 */
  421. u8 ahb_dma_mblength1; /* 0x3611 */
  422. u8 ahb_dma_stat; /* 0x3612 */
  423. u8 ahb_dma_int; /* 0x3613 */
  424. u8 ahb_dma_mask; /* 0x3614 */
  425. u8 ahb_dma_pol; /* 0x3615 */
  426. u8 ahb_dma_conf1; /* 0x3616 */
  427. u8 ahb_dma_buffstat; /* 0x3617 */
  428. u8 ahb_dma_buffint; /* 0x3618 */
  429. u8 ahb_dma_buffmask; /* 0x3619 */
  430. u8 ahb_dma_buffpol; /* 0x361a */
  431. u8 reserved20[0x9e5];
  432. /* Main Controller Registers */
  433. u8 mc_sfrdiv; /* 0x4000 */
  434. u8 mc_clkdis; /* 0x4001 */
  435. u8 mc_swrstz; /* 0x4002 */
  436. u8 mc_opctrl; /* 0x4003 */
  437. u8 mc_flowctrl; /* 0x4004 */
  438. u8 mc_phyrstz; /* 0x4005 */
  439. u8 mc_lockonclock; /* 0x4006 */
  440. u8 mc_heacphy_rst; /* 0x4007 */
  441. u8 reserved21[0xf8];
  442. /* Colorspace Converter Registers */
  443. u8 csc_cfg; /* 0x4100 */
  444. u8 csc_scale; /* 0x4101 */
  445. u8 csc_coef_a1_msb; /* 0x4102 */
  446. u8 csc_coef_a1_lsb; /* 0x4103 */
  447. u8 csc_coef_a2_msb; /* 0x4104 */
  448. u8 csc_coef_a2_lsb; /* 0x4105 */
  449. u8 csc_coef_a3_msb; /* 0x4106 */
  450. u8 csc_coef_a3_lsb; /* 0x4107 */
  451. u8 csc_coef_a4_msb; /* 0x4108 */
  452. u8 csc_coef_a4_lsb; /* 0x4109 */
  453. u8 csc_coef_b1_msb; /* 0x410a */
  454. u8 csc_coef_b1_lsb; /* 0x410b */
  455. u8 csc_coef_b2_msb; /* 0x410c */
  456. u8 csc_coef_b2_lsb; /* 0x410d */
  457. u8 csc_coef_b3_msb; /* 0x410e */
  458. u8 csc_coef_b3_lsb; /* 0x410f */
  459. u8 csc_coef_b4_msb; /* 0x4110 */
  460. u8 csc_coef_b4_lsb; /* 0x4111 */
  461. u8 csc_coef_c1_msb; /* 0x4112 */
  462. u8 csc_coef_c1_lsb; /* 0x4113 */
  463. u8 csc_coef_c2_msb; /* 0x4114 */
  464. u8 csc_coef_c2_lsb; /* 0x4115 */
  465. u8 csc_coef_c3_msb; /* 0x4116 */
  466. u8 csc_coef_c3_lsb; /* 0x4117 */
  467. u8 csc_coef_c4_msb; /* 0x4118 */
  468. u8 csc_coef_c4_lsb; /* 0x4119 */
  469. u8 reserved22[0xee6];
  470. /* HDCP Encryption Engine Registers */
  471. u8 a_hdcpcfg0; /* 0x5000 */
  472. u8 a_hdcpcfg1; /* 0x5001 */
  473. u8 a_hdcpobs0; /* 0x5002 */
  474. u8 a_hdcpobs1; /* 0x5003 */
  475. u8 a_hdcpobs2; /* 0x5004 */
  476. u8 a_hdcpobs3; /* 0x5005 */
  477. u8 a_apiintclr; /* 0x5006 */
  478. u8 a_apiintstat; /* 0x5007 */
  479. u8 a_apiintmsk; /* 0x5008 */
  480. u8 a_vidpolcfg; /* 0x5009 */
  481. u8 a_oesswcfg; /* 0x500a */
  482. u8 a_timer1setup0; /* 0x500b */
  483. u8 a_timer1setup1; /* 0x500c */
  484. u8 a_timer2setup0; /* 0x500d */
  485. u8 a_timer2setup1; /* 0x500e */
  486. u8 a_100mscfg; /* 0x500f */
  487. u8 a_2scfg0; /* 0x5010 */
  488. u8 a_2scfg1; /* 0x5011 */
  489. u8 a_5scfg0; /* 0x5012 */
  490. u8 a_5scfg1; /* 0x5013 */
  491. u8 a_srmverlsb; /* 0x5014 */
  492. u8 a_srmvermsb; /* 0x5015 */
  493. u8 a_srmctrl; /* 0x5016 */
  494. u8 a_sfrsetup; /* 0x5017 */
  495. u8 a_i2chsetup; /* 0x5018 */
  496. u8 a_intsetup; /* 0x5019 */
  497. u8 a_presetup; /* 0x501a */
  498. u8 reserved23[0x5];
  499. u8 a_srm_base; /* 0x5020 */
  500. u8 reserved24[0x2cdf];
  501. /* CEC Engine Registers */
  502. u8 cec_ctrl; /* 0x7d00 */
  503. u8 cec_stat; /* 0x7d01 */
  504. u8 cec_mask; /* 0x7d02 */
  505. u8 cec_polarity; /* 0x7d03 */
  506. u8 cec_int; /* 0x7d04 */
  507. u8 cec_addr_l; /* 0x7d05 */
  508. u8 cec_addr_h; /* 0x7d06 */
  509. u8 cec_tx_cnt; /* 0x7d07 */
  510. u8 cec_rx_cnt; /* 0x7d08 */
  511. u8 reserved25[0x7];
  512. u8 cec_tx_data0; /* 0x7d10 */
  513. u8 cec_tx_data1; /* 0x7d11 */
  514. u8 cec_tx_data2; /* 0x7d12 */
  515. u8 cec_tx_data3; /* 0x7d13 */
  516. u8 cec_tx_data4; /* 0x7d14 */
  517. u8 cec_tx_data5; /* 0x7d15 */
  518. u8 cec_tx_data6; /* 0x7d16 */
  519. u8 cec_tx_data7; /* 0x7d17 */
  520. u8 cec_tx_data8; /* 0x7d18 */
  521. u8 cec_tx_data9; /* 0x7d19 */
  522. u8 cec_tx_data10; /* 0x7d1a */
  523. u8 cec_tx_data11; /* 0x7d1b */
  524. u8 cec_tx_data12; /* 0x7d1c */
  525. u8 cec_tx_data13; /* 0x7d1d */
  526. u8 cec_tx_data14; /* 0x7d1e */
  527. u8 cec_tx_data15; /* 0x7d1f */
  528. u8 cec_rx_data0; /* 0x7d20 */
  529. u8 cec_rx_data1; /* 0x7d21 */
  530. u8 cec_rx_data2; /* 0x7d22 */
  531. u8 cec_rx_data3; /* 0x7d23 */
  532. u8 cec_rx_data4; /* 0x7d24 */
  533. u8 cec_rx_data5; /* 0x7d25 */
  534. u8 cec_rx_data6; /* 0x7d26 */
  535. u8 cec_rx_data7; /* 0x7d27 */
  536. u8 cec_rx_data8; /* 0x7d28 */
  537. u8 cec_rx_data9; /* 0x7d29 */
  538. u8 cec_rx_data10; /* 0x7d2a */
  539. u8 cec_rx_data11; /* 0x7d2b */
  540. u8 cec_rx_data12; /* 0x7d2c */
  541. u8 cec_rx_data13; /* 0x7d2d */
  542. u8 cec_rx_data14; /* 0x7d2e */
  543. u8 cec_rx_data15; /* 0x7d2f */
  544. u8 cec_lock; /* 0x7d30 */
  545. u8 cec_wkupctrl; /* 0x7d31 */
  546. u8 reserved26[0xce];
  547. /* I2C Master Registers (E-DDC) */
  548. u8 i2cm_slave; /* 0x7e00 */
  549. u8 i2cmess; /* 0x7e01 */
  550. u8 i2cm_datao; /* 0x7e02 */
  551. u8 i2cm_datai; /* 0x7e03 */
  552. u8 i2cm_operation; /* 0x7e04 */
  553. u8 i2cm_int; /* 0x7e05 */
  554. u8 i2cm_ctlint; /* 0x7e06 */
  555. u8 i2cm_div; /* 0x7e07 */
  556. u8 i2cm_segaddr; /* 0x7e08 */
  557. u8 i2cm_softrstz; /* 0x7e09 */
  558. u8 i2cm_segptr; /* 0x7e0a */
  559. u8 i2cm_ss_scl_hcnt_1_addr; /* 0x7e0b */
  560. u8 i2cm_ss_scl_hcnt_0_addr; /* 0x7e0c */
  561. u8 i2cm_ss_scl_lcnt_1_addr; /* 0x7e0d */
  562. u8 i2cm_ss_scl_lcnt_0_addr; /* 0x7e0e */
  563. u8 i2cm_fs_scl_hcnt_1_addr; /* 0x7e0f */
  564. u8 i2cm_fs_scl_hcnt_0_addr; /* 0x7e10 */
  565. u8 i2cm_fs_scl_lcnt_1_addr; /* 0x7e11 */
  566. u8 i2cm_fs_scl_lcnt_0_addr; /* 0x7e12 */
  567. u8 reserved27[0x1ed];
  568. /* Random Number Generator Registers (RNG) */
  569. u8 rng_base; /* 0x8000 */
  570. };
  571. /*
  572. * Register field definitions
  573. */
  574. enum {
  575. /* IH_FC_INT2 field values */
  576. HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
  577. HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
  578. HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
  579. /* IH_FC_STAT2 field values */
  580. HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
  581. HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
  582. HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
  583. /* IH_PHY_STAT0 field values */
  584. HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
  585. HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
  586. HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
  587. HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
  588. HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
  589. HDMI_IH_PHY_STAT0_HPD = 0x1,
  590. /* IH_MUTE_I2CMPHY_STAT0 field values */
  591. HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
  592. HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
  593. /* IH_AHBDMAAUD_STAT0 field values */
  594. HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
  595. HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
  596. HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
  597. HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
  598. HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
  599. HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
  600. /* IH_MUTE_FC_STAT2 field values */
  601. HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
  602. HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
  603. HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
  604. /* IH_MUTE_AHBDMAAUD_STAT0 field values */
  605. HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
  606. HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
  607. HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
  608. HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
  609. HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
  610. HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
  611. /* IH_MUTE field values */
  612. HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
  613. HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
  614. /* TX_INVID0 field values */
  615. HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
  616. HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
  617. HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
  618. HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
  619. HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
  620. /* TX_INSTUFFING field values */
  621. HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
  622. HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
  623. HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
  624. HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
  625. HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
  626. HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
  627. HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
  628. HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
  629. HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
  630. /* VP_PR_CD field values */
  631. HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
  632. HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
  633. HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
  634. HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
  635. /* VP_STUFF field values */
  636. HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
  637. HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
  638. HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
  639. HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
  640. HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
  641. HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
  642. HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
  643. HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
  644. HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
  645. HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
  646. HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
  647. HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
  648. HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
  649. HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
  650. HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
  651. /* VP_CONF field values */
  652. HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
  653. HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
  654. HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
  655. HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
  656. HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
  657. HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
  658. HDMI_VP_CONF_PR_EN_MASK = 0x10,
  659. HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
  660. HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
  661. HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
  662. HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
  663. HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
  664. HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
  665. HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
  666. HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
  667. HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
  668. HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
  669. HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
  670. HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
  671. /* VP_REMAP field values */
  672. HDMI_VP_REMAP_MASK = 0x3,
  673. HDMI_VP_REMAP_YCC422_24bit = 0x2,
  674. HDMI_VP_REMAP_YCC422_20bit = 0x1,
  675. HDMI_VP_REMAP_YCC422_16bit = 0x0,
  676. /* FC_INVIDCONF field values */
  677. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
  678. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
  679. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
  680. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
  681. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
  682. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
  683. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
  684. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
  685. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
  686. HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
  687. HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
  688. HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
  689. HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
  690. HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
  691. HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
  692. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
  693. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
  694. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
  695. HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
  696. HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
  697. HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
  698. /* FC_AUDICONF0 field values */
  699. HDMI_FC_AUDICONF0_CC_OFFSET = 4,
  700. HDMI_FC_AUDICONF0_CC_MASK = 0x70,
  701. HDMI_FC_AUDICONF0_CT_OFFSET = 0,
  702. HDMI_FC_AUDICONF0_CT_MASK = 0xF,
  703. /* FC_AUDICONF1 field values */
  704. HDMI_FC_AUDICONF1_SS_OFFSET = 3,
  705. HDMI_FC_AUDICONF1_SS_MASK = 0x18,
  706. HDMI_FC_AUDICONF1_SF_OFFSET = 0,
  707. HDMI_FC_AUDICONF1_SF_MASK = 0x7,
  708. /* FC_AUDICONF3 field values */
  709. HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
  710. HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
  711. HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
  712. HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
  713. HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
  714. HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
  715. /* FC_AUDSCHNLS0 field values */
  716. HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
  717. HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
  718. HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
  719. HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
  720. /* FC_AUDSCHNLS3-6 field values */
  721. HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
  722. HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
  723. HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
  724. HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
  725. HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
  726. HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
  727. HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
  728. HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
  729. HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
  730. HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
  731. HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
  732. HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
  733. HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
  734. HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
  735. HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
  736. HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
  737. /* HDMI_FC_AUDSCHNLS7 field values */
  738. HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
  739. HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
  740. /* HDMI_FC_AUDSCHNLS8 field values */
  741. HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
  742. HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
  743. HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
  744. HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
  745. /* FC_AUDSCONF field values */
  746. HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
  747. HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
  748. HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
  749. HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
  750. HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
  751. HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
  752. /* FC_STAT2 field values */
  753. HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
  754. HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
  755. HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
  756. /* FC_INT2 field values */
  757. HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
  758. HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
  759. HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
  760. /* FC_MASK2 field values */
  761. HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
  762. HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
  763. HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
  764. /* FC_PRCONF field values */
  765. HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
  766. HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
  767. HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
  768. HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
  769. /* FC_AVICONF0-FC_AVICONF3 field values */
  770. HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
  771. HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
  772. HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
  773. HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
  774. HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
  775. HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
  776. HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
  777. HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
  778. HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
  779. HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
  780. HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
  781. HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
  782. HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
  783. HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
  784. HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
  785. HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
  786. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
  787. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
  788. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
  789. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
  790. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
  791. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
  792. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
  793. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
  794. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
  795. HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
  796. HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
  797. HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
  798. HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
  799. HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
  800. HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
  801. HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
  802. HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
  803. HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
  804. HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
  805. HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
  806. HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
  807. HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
  808. HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
  809. HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
  810. HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
  811. HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
  812. HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
  813. HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
  814. HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
  815. HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
  816. HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
  817. HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
  818. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
  819. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
  820. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
  821. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
  822. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
  823. HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
  824. HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
  825. HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
  826. /* FC_DBGFORCE field values */
  827. HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
  828. HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
  829. /* PHY_CONF0 field values */
  830. HDMI_PHY_CONF0_PDZ_MASK = 0x80,
  831. HDMI_PHY_CONF0_PDZ_OFFSET = 7,
  832. HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
  833. HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
  834. HDMI_PHY_CONF0_SPARECTRL = 0x20,
  835. HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
  836. HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
  837. HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
  838. HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
  839. HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
  840. HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
  841. HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
  842. HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
  843. HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
  844. HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
  845. /* PHY_TST0 field values */
  846. HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
  847. HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
  848. HDMI_PHY_TST0_TSTEN_MASK = 0x10,
  849. HDMI_PHY_TST0_TSTEN_OFFSET = 4,
  850. HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
  851. HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
  852. /* PHY_STAT0 field values */
  853. HDMI_PHY_RX_SENSE3 = 0x80,
  854. HDMI_PHY_RX_SENSE2 = 0x40,
  855. HDMI_PHY_RX_SENSE1 = 0x20,
  856. HDMI_PHY_RX_SENSE0 = 0x10,
  857. HDMI_PHY_HPD = 0x02,
  858. HDMI_PHY_TX_PHY_LOCK = 0x01,
  859. /* PHY_I2CM_SLAVE_ADDR field values */
  860. HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
  861. HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
  862. /* PHY_I2CM_OPERATION_ADDR field values */
  863. HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
  864. HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
  865. /* HDMI_PHY_I2CM_INT_ADDR */
  866. HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
  867. HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
  868. /* HDMI_PHY_I2CM_CTLINT_ADDR */
  869. HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
  870. HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
  871. HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
  872. HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
  873. /* AUD_CTS3 field values */
  874. HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
  875. HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
  876. HDMI_AUD_CTS3_N_SHIFT_1 = 0,
  877. HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
  878. HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
  879. HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
  880. HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
  881. HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
  882. /* note that the CTS3 MANUAL bit has been removed
  883. from our part. Can't set it, will read as 0. */
  884. HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
  885. HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
  886. /* AHB_DMA_CONF0 field values */
  887. HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
  888. HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
  889. HDMI_AHB_DMA_CONF0_HBR = 0x10,
  890. HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
  891. HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
  892. HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
  893. HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
  894. HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
  895. HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
  896. HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
  897. HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
  898. /* HDMI_AHB_DMA_START field values */
  899. HDMI_AHB_DMA_START_START_OFFSET = 0,
  900. HDMI_AHB_DMA_START_START_MASK = 0x01,
  901. /* HDMI_AHB_DMA_STOP field values */
  902. HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
  903. HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
  904. /* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
  905. HDMI_AHB_DMA_DONE = 0x80,
  906. HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
  907. HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
  908. HDMI_AHB_DMA_ERROR = 0x10,
  909. HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
  910. HDMI_AHB_DMA_FIFO_FULL = 0x02,
  911. HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
  912. /* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */
  913. HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
  914. HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
  915. /* MC_CLKDIS field values */
  916. HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
  917. HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
  918. HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
  919. HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
  920. HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
  921. HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
  922. HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
  923. /* MC_SWRSTZ field values */
  924. HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
  925. /* MC_FLOWCTRL field values */
  926. HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
  927. HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
  928. HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
  929. /* MC_PHYRSTZ field values */
  930. HDMI_MC_PHYRSTZ_ASSERT = 0x0,
  931. HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
  932. /* MC_HEACPHY_RST field values */
  933. HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
  934. HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
  935. /* CSC_CFG field values */
  936. HDMI_CSC_CFG_INTMODE_MASK = 0x30,
  937. HDMI_CSC_CFG_INTMODE_OFFSET = 4,
  938. HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
  939. HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
  940. HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
  941. HDMI_CSC_CFG_DECMODE_MASK = 0x3,
  942. HDMI_CSC_CFG_DECMODE_OFFSET = 0,
  943. HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
  944. HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
  945. HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
  946. HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
  947. /* CSC_SCALE field values */
  948. HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
  949. HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
  950. HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
  951. HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
  952. HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
  953. HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
  954. /* A_HDCPCFG0 field values */
  955. HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
  956. HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
  957. HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
  958. HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
  959. HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
  960. HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
  961. HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
  962. HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
  963. HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
  964. HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
  965. HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
  966. HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
  967. HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
  968. HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
  969. HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
  970. HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
  971. HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
  972. HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
  973. HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
  974. HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
  975. HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
  976. HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
  977. HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
  978. HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
  979. /* A_HDCPCFG1 field values */
  980. HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
  981. HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
  982. HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
  983. HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
  984. HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
  985. HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
  986. HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
  987. HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
  988. HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
  989. HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
  990. HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
  991. /* A_VIDPOLCFG field values */
  992. HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
  993. HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
  994. HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
  995. HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
  996. HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
  997. HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
  998. HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
  999. HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
  1000. HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
  1001. HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
  1002. HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
  1003. };
  1004. #endif /* __MXC_HDMI_H__ */