mx6q-ddr.h 2.4 KB

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  1. /*
  2. * Copyright (C) 2013 Boundary Devices Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. * You should have received a copy of the GNU General Public License along
  13. * with this program; if not, write to the Free Software Foundation, Inc.,
  14. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  15. */
  16. #ifndef __ASM_ARCH_MX6Q_DDR_H__
  17. #define __ASM_ARCH_MX6Q_DDR_H__
  18. #ifndef CONFIG_MX6Q
  19. #error "wrong CPU"
  20. #endif
  21. #define MX6_IOM_DRAM_DQM0 0x020e05ac
  22. #define MX6_IOM_DRAM_DQM1 0x020e05b4
  23. #define MX6_IOM_DRAM_DQM2 0x020e0528
  24. #define MX6_IOM_DRAM_DQM3 0x020e0520
  25. #define MX6_IOM_DRAM_DQM4 0x020e0514
  26. #define MX6_IOM_DRAM_DQM5 0x020e0510
  27. #define MX6_IOM_DRAM_DQM6 0x020e05bc
  28. #define MX6_IOM_DRAM_DQM7 0x020e05c4
  29. #define MX6_IOM_DRAM_CAS 0x020e056c
  30. #define MX6_IOM_DRAM_RAS 0x020e0578
  31. #define MX6_IOM_DRAM_RESET 0x020e057c
  32. #define MX6_IOM_DRAM_SDCLK_0 0x020e0588
  33. #define MX6_IOM_DRAM_SDCLK_1 0x020e0594
  34. #define MX6_IOM_DRAM_SDBA2 0x020e058c
  35. #define MX6_IOM_DRAM_SDCKE0 0x020e0590
  36. #define MX6_IOM_DRAM_SDCKE1 0x020e0598
  37. #define MX6_IOM_DRAM_SDODT0 0x020e059c
  38. #define MX6_IOM_DRAM_SDODT1 0x020e05a0
  39. #define MX6_IOM_DRAM_SDQS0 0x020e05a8
  40. #define MX6_IOM_DRAM_SDQS1 0x020e05b0
  41. #define MX6_IOM_DRAM_SDQS2 0x020e0524
  42. #define MX6_IOM_DRAM_SDQS3 0x020e051c
  43. #define MX6_IOM_DRAM_SDQS4 0x020e0518
  44. #define MX6_IOM_DRAM_SDQS5 0x020e050c
  45. #define MX6_IOM_DRAM_SDQS6 0x020e05b8
  46. #define MX6_IOM_DRAM_SDQS7 0x020e05c0
  47. #define MX6_IOM_GRP_B0DS 0x020e0784
  48. #define MX6_IOM_GRP_B1DS 0x020e0788
  49. #define MX6_IOM_GRP_B2DS 0x020e0794
  50. #define MX6_IOM_GRP_B3DS 0x020e079c
  51. #define MX6_IOM_GRP_B4DS 0x020e07a0
  52. #define MX6_IOM_GRP_B5DS 0x020e07a4
  53. #define MX6_IOM_GRP_B6DS 0x020e07a8
  54. #define MX6_IOM_GRP_B7DS 0x020e0748
  55. #define MX6_IOM_GRP_ADDDS 0x020e074c
  56. #define MX6_IOM_DDRMODE_CTL 0x020e0750
  57. #define MX6_IOM_GRP_DDRPKE 0x020e0758
  58. #define MX6_IOM_GRP_DDRMODE 0x020e0774
  59. #define MX6_IOM_GRP_CTLDS 0x020e078c
  60. #define MX6_IOM_GRP_DDR_TYPE 0x020e0798
  61. #endif /*__ASM_ARCH_MX6Q_DDR_H__ */