mx6dl-ddr.h 2.4 KB

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  1. /*
  2. * Copyright (C) 2013 Boundary Devices Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. * You should have received a copy of the GNU General Public License along
  13. * with this program; if not, write to the Free Software Foundation, Inc.,
  14. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  15. */
  16. #ifndef __ASM_ARCH_MX6DLS_DDR_H__
  17. #define __ASM_ARCH_MX6DLS_DDR_H__
  18. #ifndef CONFIG_MX6DL
  19. #ifndef CONFIG_MX6S
  20. #error "wrong CPU"
  21. #endif
  22. #endif
  23. #define MX6_IOM_DRAM_DQM0 0x020e0470
  24. #define MX6_IOM_DRAM_DQM1 0x020e0474
  25. #define MX6_IOM_DRAM_DQM2 0x020e0478
  26. #define MX6_IOM_DRAM_DQM3 0x020e047c
  27. #define MX6_IOM_DRAM_DQM4 0x020e0480
  28. #define MX6_IOM_DRAM_DQM5 0x020e0484
  29. #define MX6_IOM_DRAM_DQM6 0x020e0488
  30. #define MX6_IOM_DRAM_DQM7 0x020e048c
  31. #define MX6_IOM_DRAM_CAS 0x020e0464
  32. #define MX6_IOM_DRAM_RAS 0x020e0490
  33. #define MX6_IOM_DRAM_RESET 0x020e0494
  34. #define MX6_IOM_DRAM_SDCLK_0 0x020e04ac
  35. #define MX6_IOM_DRAM_SDCLK_1 0x020e04b0
  36. #define MX6_IOM_DRAM_SDBA2 0x020e04a0
  37. #define MX6_IOM_DRAM_SDCKE0 0x020e04a4
  38. #define MX6_IOM_DRAM_SDCKE1 0x020e04a8
  39. #define MX6_IOM_DRAM_SDODT0 0x020e04b4
  40. #define MX6_IOM_DRAM_SDODT1 0x020e04b8
  41. #define MX6_IOM_DRAM_SDQS0 0x020e04bc
  42. #define MX6_IOM_DRAM_SDQS1 0x020e04c0
  43. #define MX6_IOM_DRAM_SDQS2 0x020e04c4
  44. #define MX6_IOM_DRAM_SDQS3 0x020e04c8
  45. #define MX6_IOM_DRAM_SDQS4 0x020e04cc
  46. #define MX6_IOM_DRAM_SDQS5 0x020e04d0
  47. #define MX6_IOM_DRAM_SDQS6 0x020e04d4
  48. #define MX6_IOM_DRAM_SDQS7 0x020e04d8
  49. #define MX6_IOM_GRP_B0DS 0x020e0764
  50. #define MX6_IOM_GRP_B1DS 0x020e0770
  51. #define MX6_IOM_GRP_B2DS 0x020e0778
  52. #define MX6_IOM_GRP_B3DS 0x020e077c
  53. #define MX6_IOM_GRP_B4DS 0x020e0780
  54. #define MX6_IOM_GRP_B5DS 0x020e0784
  55. #define MX6_IOM_GRP_B6DS 0x020e078c
  56. #define MX6_IOM_GRP_B7DS 0x020e0748
  57. #define MX6_IOM_GRP_ADDDS 0x020e074c
  58. #define MX6_IOM_DDRMODE_CTL 0x020e0750
  59. #define MX6_IOM_GRP_DDRPKE 0x020e0754
  60. #define MX6_IOM_GRP_DDRMODE 0x020e0760
  61. #define MX6_IOM_GRP_CTLDS 0x020e076c
  62. #define MX6_IOM_GRP_DDR_TYPE 0x020e0774
  63. #endif /*__ASM_ARCH_MX6S_DDR_H__ */