imx-regs.h 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613
  1. /*
  2. * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. * You should have received a copy of the GNU General Public License along
  13. * with this program; if not, write to the Free Software Foundation, Inc.,
  14. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  15. */
  16. #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
  17. #define __ASM_ARCH_MX6_IMX_REGS_H__
  18. #define ARCH_MXC
  19. #define CONFIG_SYS_CACHELINE_SIZE 32
  20. #define ROMCP_ARB_BASE_ADDR 0x00000000
  21. #define ROMCP_ARB_END_ADDR 0x000FFFFF
  22. #define CAAM_ARB_BASE_ADDR 0x00100000
  23. #define CAAM_ARB_END_ADDR 0x00103FFF
  24. #define APBH_DMA_ARB_BASE_ADDR 0x00110000
  25. #define APBH_DMA_ARB_END_ADDR 0x00117FFF
  26. #define HDMI_ARB_BASE_ADDR 0x00120000
  27. #define HDMI_ARB_END_ADDR 0x00128FFF
  28. #define GPU_3D_ARB_BASE_ADDR 0x00130000
  29. #define GPU_3D_ARB_END_ADDR 0x00133FFF
  30. #define GPU_2D_ARB_BASE_ADDR 0x00134000
  31. #define GPU_2D_ARB_END_ADDR 0x00137FFF
  32. #define DTCP_ARB_BASE_ADDR 0x00138000
  33. #define DTCP_ARB_END_ADDR 0x0013BFFF
  34. /* GPV - PL301 configuration ports */
  35. #define GPV2_BASE_ADDR 0x00200000
  36. #define GPV3_BASE_ADDR 0x00300000
  37. #define GPV4_BASE_ADDR 0x00800000
  38. #define IRAM_BASE_ADDR 0x00900000
  39. #define SCU_BASE_ADDR 0x00A00000
  40. #define IC_INTERFACES_BASE_ADDR 0x00A00100
  41. #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
  42. #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
  43. #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
  44. #define GPV0_BASE_ADDR 0x00B00000
  45. #define GPV1_BASE_ADDR 0x00C00000
  46. #define PCIE_ARB_BASE_ADDR 0x01000000
  47. #define PCIE_ARB_END_ADDR 0x01FFFFFF
  48. #define AIPS1_ARB_BASE_ADDR 0x02000000
  49. #define AIPS1_ARB_END_ADDR 0x020FFFFF
  50. #define AIPS2_ARB_BASE_ADDR 0x02100000
  51. #define AIPS2_ARB_END_ADDR 0x021FFFFF
  52. #define SATA_ARB_BASE_ADDR 0x02200000
  53. #define SATA_ARB_END_ADDR 0x02203FFF
  54. #define OPENVG_ARB_BASE_ADDR 0x02204000
  55. #define OPENVG_ARB_END_ADDR 0x02207FFF
  56. #define HSI_ARB_BASE_ADDR 0x02208000
  57. #define HSI_ARB_END_ADDR 0x0220BFFF
  58. #define IPU1_ARB_BASE_ADDR 0x02400000
  59. #define IPU1_ARB_END_ADDR 0x027FFFFF
  60. #define IPU2_ARB_BASE_ADDR 0x02800000
  61. #define IPU2_ARB_END_ADDR 0x02BFFFFF
  62. #define WEIM_ARB_BASE_ADDR 0x08000000
  63. #define WEIM_ARB_END_ADDR 0x0FFFFFFF
  64. #define MMDC0_ARB_BASE_ADDR 0x10000000
  65. #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
  66. #define MMDC1_ARB_BASE_ADDR 0x80000000
  67. #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
  68. #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
  69. #define IPU_SOC_OFFSET 0x00200000
  70. /* Defines for Blocks connected via AIPS (SkyBlue) */
  71. #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
  72. #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
  73. #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
  74. #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
  75. #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
  76. #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
  77. #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
  78. #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
  79. #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
  80. #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
  81. #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
  82. #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
  83. #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
  84. #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
  85. #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
  86. #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
  87. #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
  88. #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
  89. #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
  90. #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
  91. #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
  92. #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
  93. #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
  94. #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
  95. #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
  96. #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
  97. #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
  98. #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
  99. #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
  100. #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
  101. #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
  102. #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
  103. #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
  104. #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
  105. #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
  106. #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
  107. #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
  108. #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
  109. #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
  110. #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
  111. #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
  112. #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
  113. #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
  114. #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
  115. #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
  116. #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
  117. #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
  118. #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
  119. #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
  120. #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
  121. #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
  122. #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
  123. #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
  124. #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
  125. #define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
  126. #define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
  127. #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
  128. #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
  129. #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
  130. #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
  131. #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
  132. #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
  133. #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
  134. #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
  135. #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
  136. #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
  137. #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
  138. #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
  139. #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
  140. #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
  141. #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
  142. #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
  143. #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
  144. #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
  145. #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
  146. #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
  147. #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
  148. #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
  149. #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
  150. #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
  151. #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
  152. #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
  153. #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
  154. #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
  155. #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
  156. #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
  157. #define CHIP_REV_1_0 0x10
  158. #define IRAM_SIZE 0x00040000
  159. #define IMX_IIM_BASE OCOTP_BASE_ADDR
  160. #define FEC_QUIRK_ENET_MAC
  161. #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  162. #include <asm/types.h>
  163. extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
  164. /* System Reset Controller (SRC) */
  165. struct src {
  166. u32 scr;
  167. u32 sbmr1;
  168. u32 srsr;
  169. u32 reserved1[2];
  170. u32 sisr;
  171. u32 simr;
  172. u32 sbmr2;
  173. u32 gpr1;
  174. u32 gpr2;
  175. u32 gpr3;
  176. u32 gpr4;
  177. u32 gpr5;
  178. u32 gpr6;
  179. u32 gpr7;
  180. u32 gpr8;
  181. u32 gpr9;
  182. u32 gpr10;
  183. };
  184. /* OCOTP Registers */
  185. struct ocotp_regs {
  186. u32 reserved[0x198];
  187. u32 gp1; /* 0x660 */
  188. };
  189. /* GPR3 bitfields */
  190. #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
  191. #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
  192. #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
  193. #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
  194. #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
  195. #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
  196. #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
  197. #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
  198. #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
  199. #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
  200. #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
  201. #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
  202. #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
  203. #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
  204. #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
  205. #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
  206. #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
  207. #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
  208. #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
  209. #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
  210. #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
  211. #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
  212. #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
  213. #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
  214. #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
  215. #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
  216. #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
  217. #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
  218. #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
  219. #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
  220. #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
  221. #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
  222. #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
  223. #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
  224. #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
  225. #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
  226. #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
  227. #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
  228. #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
  229. #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
  230. struct iomuxc {
  231. u32 gpr[14];
  232. u32 omux[5];
  233. /* mux and pad registers */
  234. };
  235. #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
  236. #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
  237. #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
  238. #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
  239. #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
  240. #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
  241. #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
  242. #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
  243. #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
  244. #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
  245. #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
  246. #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
  247. #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
  248. #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
  249. #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
  250. #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
  251. #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
  252. #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
  253. #define IOMUXC_GPR2_BITMAP_SPWG 0
  254. #define IOMUXC_GPR2_BITMAP_JEIDA 1
  255. #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
  256. #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
  257. #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
  258. #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
  259. #define IOMUXC_GPR2_DATA_WIDTH_18 0
  260. #define IOMUXC_GPR2_DATA_WIDTH_24 1
  261. #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
  262. #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
  263. #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
  264. #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
  265. #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
  266. #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
  267. #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
  268. #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
  269. #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
  270. #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
  271. #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
  272. #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
  273. #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
  274. #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
  275. #define IOMUXC_GPR2_MODE_DISABLED 0
  276. #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
  277. #define IOMUXC_GPR2_MODE_ENABLED_DI1 2
  278. #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
  279. #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
  280. #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
  281. #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
  282. #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
  283. #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
  284. #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  285. #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  286. #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  287. #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
  288. /* ECSPI registers */
  289. struct cspi_regs {
  290. u32 rxdata;
  291. u32 txdata;
  292. u32 ctrl;
  293. u32 cfg;
  294. u32 intr;
  295. u32 dma;
  296. u32 stat;
  297. u32 period;
  298. };
  299. /*
  300. * CSPI register definitions
  301. */
  302. #define MXC_ECSPI
  303. #define MXC_CSPICTRL_EN (1 << 0)
  304. #define MXC_CSPICTRL_MODE (1 << 1)
  305. #define MXC_CSPICTRL_XCH (1 << 2)
  306. #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
  307. #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
  308. #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
  309. #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
  310. #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
  311. #define MXC_CSPICTRL_MAXBITS 0xfff
  312. #define MXC_CSPICTRL_TC (1 << 7)
  313. #define MXC_CSPICTRL_RXOVF (1 << 6)
  314. #define MXC_CSPIPERIOD_32KHZ (1 << 15)
  315. #define MAX_SPI_BYTES 32
  316. /* Bit position inside CTRL register to be associated with SS */
  317. #define MXC_CSPICTRL_CHAN 18
  318. /* Bit position inside CON register to be associated with SS */
  319. #define MXC_CSPICON_POL 4
  320. #define MXC_CSPICON_PHA 0
  321. #define MXC_CSPICON_SSPOL 12
  322. #define MXC_SPI_BASE_ADDRESSES \
  323. ECSPI1_BASE_ADDR, \
  324. ECSPI2_BASE_ADDR, \
  325. ECSPI3_BASE_ADDR, \
  326. ECSPI4_BASE_ADDR, \
  327. ECSPI5_BASE_ADDR
  328. struct iim_regs {
  329. u32 ctrl;
  330. u32 ctrl_set;
  331. u32 ctrl_clr;
  332. u32 ctrl_tog;
  333. u32 timing;
  334. u32 rsvd0[3];
  335. u32 data;
  336. u32 rsvd1[3];
  337. u32 read_ctrl;
  338. u32 rsvd2[3];
  339. u32 fuse_data;
  340. u32 rsvd3[3];
  341. u32 sticky;
  342. u32 rsvd4[3];
  343. u32 scs;
  344. u32 scs_set;
  345. u32 scs_clr;
  346. u32 scs_tog;
  347. u32 crc_addr;
  348. u32 rsvd5[3];
  349. u32 crc_value;
  350. u32 rsvd6[3];
  351. u32 version;
  352. u32 rsvd7[0xdb];
  353. struct fuse_bank {
  354. u32 fuse_regs[0x20];
  355. } bank[15];
  356. };
  357. struct fuse_bank4_regs {
  358. u32 sjc_resp_low;
  359. u32 rsvd0[3];
  360. u32 sjc_resp_high;
  361. u32 rsvd1[3];
  362. u32 mac_addr_low;
  363. u32 rsvd2[3];
  364. u32 mac_addr_high;
  365. u32 rsvd3[0x13];
  366. };
  367. struct aipstz_regs {
  368. u32 mprot0;
  369. u32 mprot1;
  370. u32 rsvd[0xe];
  371. u32 opacr0;
  372. u32 opacr1;
  373. u32 opacr2;
  374. u32 opacr3;
  375. u32 opacr4;
  376. };
  377. struct anatop_regs {
  378. u32 pll_sys; /* 0x000 */
  379. u32 pll_sys_set; /* 0x004 */
  380. u32 pll_sys_clr; /* 0x008 */
  381. u32 pll_sys_tog; /* 0x00c */
  382. u32 usb1_pll_480_ctrl; /* 0x010 */
  383. u32 usb1_pll_480_ctrl_set; /* 0x014 */
  384. u32 usb1_pll_480_ctrl_clr; /* 0x018 */
  385. u32 usb1_pll_480_ctrl_tog; /* 0x01c */
  386. u32 usb2_pll_480_ctrl; /* 0x020 */
  387. u32 usb2_pll_480_ctrl_set; /* 0x024 */
  388. u32 usb2_pll_480_ctrl_clr; /* 0x028 */
  389. u32 usb2_pll_480_ctrl_tog; /* 0x02c */
  390. u32 pll_528; /* 0x030 */
  391. u32 pll_528_set; /* 0x034 */
  392. u32 pll_528_clr; /* 0x038 */
  393. u32 pll_528_tog; /* 0x03c */
  394. u32 pll_528_ss; /* 0x040 */
  395. u32 rsvd0[3];
  396. u32 pll_528_num; /* 0x050 */
  397. u32 rsvd1[3];
  398. u32 pll_528_denom; /* 0x060 */
  399. u32 rsvd2[3];
  400. u32 pll_audio; /* 0x070 */
  401. u32 pll_audio_set; /* 0x074 */
  402. u32 pll_audio_clr; /* 0x078 */
  403. u32 pll_audio_tog; /* 0x07c */
  404. u32 pll_audio_num; /* 0x080 */
  405. u32 rsvd3[3];
  406. u32 pll_audio_denom; /* 0x090 */
  407. u32 rsvd4[3];
  408. u32 pll_video; /* 0x0a0 */
  409. u32 pll_video_set; /* 0x0a4 */
  410. u32 pll_video_clr; /* 0x0a8 */
  411. u32 pll_video_tog; /* 0x0ac */
  412. u32 pll_video_num; /* 0x0b0 */
  413. u32 rsvd5[3];
  414. u32 pll_video_denom; /* 0x0c0 */
  415. u32 rsvd6[3];
  416. u32 pll_mlb; /* 0x0d0 */
  417. u32 pll_mlb_set; /* 0x0d4 */
  418. u32 pll_mlb_clr; /* 0x0d8 */
  419. u32 pll_mlb_tog; /* 0x0dc */
  420. u32 pll_enet; /* 0x0e0 */
  421. u32 pll_enet_set; /* 0x0e4 */
  422. u32 pll_enet_clr; /* 0x0e8 */
  423. u32 pll_enet_tog; /* 0x0ec */
  424. u32 pfd_480; /* 0x0f0 */
  425. u32 pfd_480_set; /* 0x0f4 */
  426. u32 pfd_480_clr; /* 0x0f8 */
  427. u32 pfd_480_tog; /* 0x0fc */
  428. u32 pfd_528; /* 0x100 */
  429. u32 pfd_528_set; /* 0x104 */
  430. u32 pfd_528_clr; /* 0x108 */
  431. u32 pfd_528_tog; /* 0x10c */
  432. u32 reg_1p1; /* 0x110 */
  433. u32 reg_1p1_set; /* 0x114 */
  434. u32 reg_1p1_clr; /* 0x118 */
  435. u32 reg_1p1_tog; /* 0x11c */
  436. u32 reg_3p0; /* 0x120 */
  437. u32 reg_3p0_set; /* 0x124 */
  438. u32 reg_3p0_clr; /* 0x128 */
  439. u32 reg_3p0_tog; /* 0x12c */
  440. u32 reg_2p5; /* 0x130 */
  441. u32 reg_2p5_set; /* 0x134 */
  442. u32 reg_2p5_clr; /* 0x138 */
  443. u32 reg_2p5_tog; /* 0x13c */
  444. u32 reg_core; /* 0x140 */
  445. u32 reg_core_set; /* 0x144 */
  446. u32 reg_core_clr; /* 0x148 */
  447. u32 reg_core_tog; /* 0x14c */
  448. u32 ana_misc0; /* 0x150 */
  449. u32 ana_misc0_set; /* 0x154 */
  450. u32 ana_misc0_clr; /* 0x158 */
  451. u32 ana_misc0_tog; /* 0x15c */
  452. u32 ana_misc1; /* 0x160 */
  453. u32 ana_misc1_set; /* 0x164 */
  454. u32 ana_misc1_clr; /* 0x168 */
  455. u32 ana_misc1_tog; /* 0x16c */
  456. u32 ana_misc2; /* 0x170 */
  457. u32 ana_misc2_set; /* 0x174 */
  458. u32 ana_misc2_clr; /* 0x178 */
  459. u32 ana_misc2_tog; /* 0x17c */
  460. u32 tempsense0; /* 0x180 */
  461. u32 tempsense0_set; /* 0x184 */
  462. u32 tempsense0_clr; /* 0x188 */
  463. u32 tempsense0_tog; /* 0x18c */
  464. u32 tempsense1; /* 0x190 */
  465. u32 tempsense1_set; /* 0x194 */
  466. u32 tempsense1_clr; /* 0x198 */
  467. u32 tempsense1_tog; /* 0x19c */
  468. u32 usb1_vbus_detect; /* 0x1a0 */
  469. u32 usb1_vbus_detect_set; /* 0x1a4 */
  470. u32 usb1_vbus_detect_clr; /* 0x1a8 */
  471. u32 usb1_vbus_detect_tog; /* 0x1ac */
  472. u32 usb1_chrg_detect; /* 0x1b0 */
  473. u32 usb1_chrg_detect_set; /* 0x1b4 */
  474. u32 usb1_chrg_detect_clr; /* 0x1b8 */
  475. u32 usb1_chrg_detect_tog; /* 0x1bc */
  476. u32 usb1_vbus_det_stat; /* 0x1c0 */
  477. u32 usb1_vbus_det_stat_set; /* 0x1c4 */
  478. u32 usb1_vbus_det_stat_clr; /* 0x1c8 */
  479. u32 usb1_vbus_det_stat_tog; /* 0x1cc */
  480. u32 usb1_chrg_det_stat; /* 0x1d0 */
  481. u32 usb1_chrg_det_stat_set; /* 0x1d4 */
  482. u32 usb1_chrg_det_stat_clr; /* 0x1d8 */
  483. u32 usb1_chrg_det_stat_tog; /* 0x1dc */
  484. u32 usb1_loopback; /* 0x1e0 */
  485. u32 usb1_loopback_set; /* 0x1e4 */
  486. u32 usb1_loopback_clr; /* 0x1e8 */
  487. u32 usb1_loopback_tog; /* 0x1ec */
  488. u32 usb1_misc; /* 0x1f0 */
  489. u32 usb1_misc_set; /* 0x1f4 */
  490. u32 usb1_misc_clr; /* 0x1f8 */
  491. u32 usb1_misc_tog; /* 0x1fc */
  492. u32 usb2_vbus_detect; /* 0x200 */
  493. u32 usb2_vbus_detect_set; /* 0x204 */
  494. u32 usb2_vbus_detect_clr; /* 0x208 */
  495. u32 usb2_vbus_detect_tog; /* 0x20c */
  496. u32 usb2_chrg_detect; /* 0x210 */
  497. u32 usb2_chrg_detect_set; /* 0x214 */
  498. u32 usb2_chrg_detect_clr; /* 0x218 */
  499. u32 usb2_chrg_detect_tog; /* 0x21c */
  500. u32 usb2_vbus_det_stat; /* 0x220 */
  501. u32 usb2_vbus_det_stat_set; /* 0x224 */
  502. u32 usb2_vbus_det_stat_clr; /* 0x228 */
  503. u32 usb2_vbus_det_stat_tog; /* 0x22c */
  504. u32 usb2_chrg_det_stat; /* 0x230 */
  505. u32 usb2_chrg_det_stat_set; /* 0x234 */
  506. u32 usb2_chrg_det_stat_clr; /* 0x238 */
  507. u32 usb2_chrg_det_stat_tog; /* 0x23c */
  508. u32 usb2_loopback; /* 0x240 */
  509. u32 usb2_loopback_set; /* 0x244 */
  510. u32 usb2_loopback_clr; /* 0x248 */
  511. u32 usb2_loopback_tog; /* 0x24c */
  512. u32 usb2_misc; /* 0x250 */
  513. u32 usb2_misc_set; /* 0x254 */
  514. u32 usb2_misc_clr; /* 0x258 */
  515. u32 usb2_misc_tog; /* 0x25c */
  516. u32 digprog; /* 0x260 */
  517. u32 reserved1[7];
  518. u32 digprog_sololite; /* 0x280 */
  519. };
  520. #define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
  521. #define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
  522. #define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
  523. #define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
  524. #define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
  525. #define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
  526. #define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
  527. #define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
  528. #define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
  529. #define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
  530. #define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
  531. #define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
  532. #define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
  533. #define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
  534. #define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
  535. #define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
  536. #define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
  537. #define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
  538. #define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
  539. #define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
  540. #define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
  541. #define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
  542. #define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
  543. struct iomuxc_base_regs {
  544. u32 gpr[14]; /* 0x000 */
  545. u32 obsrv[5]; /* 0x038 */
  546. u32 swmux_ctl[197]; /* 0x04c */
  547. u32 swpad_ctl[250]; /* 0x360 */
  548. u32 swgrp[26]; /* 0x748 */
  549. u32 daisy[104]; /* 0x7b0..94c */
  550. };
  551. struct wdog_regs {
  552. u16 wcr; /* Control */
  553. u16 wsr; /* Service */
  554. u16 wrsr; /* Reset Status */
  555. u16 wicr; /* Interrupt Control */
  556. u16 wmcr; /* Miscellaneous Control */
  557. };
  558. #endif /* __ASSEMBLER__*/
  559. #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */