crm_regs.h 40 KB

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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  17. *
  18. */
  19. #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
  20. #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
  21. #define CCM_CCGR0 0x020C4068
  22. #define CCM_CCGR1 0x020C406c
  23. #define CCM_CCGR2 0x020C4070
  24. #define CCM_CCGR3 0x020C4074
  25. #define CCM_CCGR4 0x020C4078
  26. #define CCM_CCGR5 0x020C407c
  27. #define CCM_CCGR6 0x020C4080
  28. #define PMU_MISC2 0x020C8170
  29. #ifndef __ASSEMBLY__
  30. struct mxc_ccm_reg {
  31. u32 ccr; /* 0x0000 */
  32. u32 ccdr;
  33. u32 csr;
  34. u32 ccsr;
  35. u32 cacrr; /* 0x0010*/
  36. u32 cbcdr;
  37. u32 cbcmr;
  38. u32 cscmr1;
  39. u32 cscmr2; /* 0x0020 */
  40. u32 cscdr1;
  41. u32 cs1cdr;
  42. u32 cs2cdr;
  43. u32 cdcdr; /* 0x0030 */
  44. u32 chsccdr;
  45. u32 cscdr2;
  46. u32 cscdr3;
  47. u32 cscdr4; /* 0x0040 */
  48. u32 resv0;
  49. u32 cdhipr;
  50. u32 cdcr;
  51. u32 ctor; /* 0x0050 */
  52. u32 clpcr;
  53. u32 cisr;
  54. u32 cimr;
  55. u32 ccosr; /* 0x0060 */
  56. u32 cgpr;
  57. u32 CCGR0;
  58. u32 CCGR1;
  59. u32 CCGR2; /* 0x0070 */
  60. u32 CCGR3;
  61. u32 CCGR4;
  62. u32 CCGR5;
  63. u32 CCGR6; /* 0x0080 */
  64. u32 CCGR7;
  65. u32 cmeor;
  66. u32 resv[0xfdd];
  67. u32 analog_pll_sys; /* 0x4000 */
  68. u32 analog_pll_sys_set;
  69. u32 analog_pll_sys_clr;
  70. u32 analog_pll_sys_tog;
  71. u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
  72. u32 analog_usb1_pll_480_ctrl_set;
  73. u32 analog_usb1_pll_480_ctrl_clr;
  74. u32 analog_usb1_pll_480_ctrl_tog;
  75. u32 analog_reserved0[4];
  76. u32 analog_pll_528; /* 0x4030 */
  77. u32 analog_pll_528_set;
  78. u32 analog_pll_528_clr;
  79. u32 analog_pll_528_tog;
  80. u32 analog_pll_528_ss; /* 0x4040 */
  81. u32 analog_reserved1[3];
  82. u32 analog_pll_528_num; /* 0x4050 */
  83. u32 analog_reserved2[3];
  84. u32 analog_pll_528_denom; /* 0x4060 */
  85. u32 analog_reserved3[3];
  86. u32 analog_pll_audio; /* 0x4070 */
  87. u32 analog_pll_audio_set;
  88. u32 analog_pll_audio_clr;
  89. u32 analog_pll_audio_tog;
  90. u32 analog_pll_audio_num; /* 0x4080*/
  91. u32 analog_reserved4[3];
  92. u32 analog_pll_audio_denom; /* 0x4090 */
  93. u32 analog_reserved5[3];
  94. u32 analog_pll_video; /* 0x40a0 */
  95. u32 analog_pll_video_set;
  96. u32 analog_pll_video_clr;
  97. u32 analog_pll_video_tog;
  98. u32 analog_pll_video_num; /* 0x40b0 */
  99. u32 analog_reserved6[3];
  100. u32 analog_pll_vedio_denon; /* 0x40c0 */
  101. u32 analog_reserved7[7];
  102. u32 analog_pll_enet; /* 0x40e0 */
  103. u32 analog_pll_enet_set;
  104. u32 analog_pll_enet_clr;
  105. u32 analog_pll_enet_tog;
  106. u32 analog_pfd_480; /* 0x40f0 */
  107. u32 analog_pfd_480_set;
  108. u32 analog_pfd_480_clr;
  109. u32 analog_pfd_480_tog;
  110. u32 analog_pfd_528; /* 0x4100 */
  111. u32 analog_pfd_528_set;
  112. u32 analog_pfd_528_clr;
  113. u32 analog_pfd_528_tog;
  114. };
  115. #endif
  116. /* Define the bits in register CCR */
  117. #define MXC_CCM_CCR_RBC_EN (1 << 27)
  118. #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
  119. #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
  120. #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
  121. #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
  122. #define MXC_CCM_CCR_COSC_EN (1 << 12)
  123. #define MXC_CCM_CCR_OSCNT_MASK 0xFF
  124. #define MXC_CCM_CCR_OSCNT_OFFSET 0
  125. /* Define the bits in register CCDR */
  126. #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
  127. #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
  128. /* Define the bits in register CSR */
  129. #define MXC_CCM_CSR_COSC_READY (1 << 5)
  130. #define MXC_CCM_CSR_REF_EN_B (1 << 0)
  131. /* Define the bits in register CCSR */
  132. #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
  133. #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
  134. #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
  135. #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
  136. #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
  137. #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
  138. #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
  139. #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
  140. #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
  141. #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
  142. #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
  143. /* Define the bits in register CACRR */
  144. #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
  145. #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
  146. /* Define the bits in register CBCDR */
  147. #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
  148. #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
  149. #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
  150. #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
  151. #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
  152. #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
  153. #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
  154. #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
  155. #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
  156. #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
  157. #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
  158. #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
  159. #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
  160. #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
  161. #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
  162. #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
  163. #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
  164. #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
  165. /* Define the bits in register CBCMR */
  166. #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
  167. #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
  168. #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
  169. #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
  170. #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
  171. #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
  172. #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
  173. #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
  174. #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
  175. #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
  176. #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
  177. #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
  178. #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
  179. #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
  180. #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
  181. #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
  182. #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
  183. #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
  184. #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
  185. #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
  186. #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
  187. #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
  188. #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
  189. #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
  190. #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
  191. /* Define the bits in register CSCMR1 */
  192. #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
  193. #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
  194. #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
  195. #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
  196. #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
  197. #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
  198. #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
  199. #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
  200. #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
  201. #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
  202. #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
  203. #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
  204. #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
  205. #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
  206. #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
  207. #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
  208. #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
  209. #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
  210. #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
  211. /* Define the bits in register CSCMR2 */
  212. #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
  213. #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
  214. #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
  215. #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
  216. #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
  217. #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
  218. /* Define the bits in register CSCDR1 */
  219. #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
  220. #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
  221. #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
  222. #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
  223. #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
  224. #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
  225. #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
  226. #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
  227. #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
  228. #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
  229. #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
  230. #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
  231. #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
  232. #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
  233. #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
  234. #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
  235. /* Define the bits in register CS1CDR */
  236. #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
  237. #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
  238. #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
  239. #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
  240. #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
  241. #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
  242. #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
  243. #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
  244. #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
  245. #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
  246. /* Define the bits in register CS2CDR */
  247. #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
  248. #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
  249. #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
  250. #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
  251. #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
  252. #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
  253. #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
  254. #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
  255. #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
  256. #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
  257. #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
  258. #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
  259. #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
  260. #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
  261. /* Define the bits in register CDCDR */
  262. #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
  263. #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
  264. #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
  265. #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
  266. #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
  267. #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
  268. #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19
  269. #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
  270. #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
  271. #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
  272. #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
  273. #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
  274. #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
  275. #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
  276. #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
  277. /* Define the bits in register CHSCCDR */
  278. #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
  279. #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
  280. #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
  281. #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
  282. #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
  283. #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
  284. #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
  285. #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
  286. #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
  287. #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
  288. #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
  289. #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
  290. #define CHSCCDR_CLK_SEL_LDB_DI0 3
  291. #define CHSCCDR_PODF_DIVIDE_BY_3 2
  292. #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
  293. /* Define the bits in register CSCDR2 */
  294. #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
  295. #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
  296. #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
  297. #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
  298. #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
  299. #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
  300. #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
  301. #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
  302. #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
  303. #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
  304. #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
  305. #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
  306. #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
  307. #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
  308. /* Define the bits in register CSCDR3 */
  309. #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
  310. #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
  311. #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
  312. #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
  313. #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
  314. #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
  315. #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
  316. #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
  317. /* Define the bits in register CDHIPR */
  318. #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
  319. #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
  320. #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
  321. #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
  322. #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
  323. #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
  324. #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
  325. /* Define the bits in register CLPCR */
  326. #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
  327. #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
  328. #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
  329. #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
  330. #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
  331. #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
  332. #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
  333. #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
  334. #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
  335. #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
  336. #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
  337. #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
  338. #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
  339. #define MXC_CCM_CLPCR_VSTBY (1 << 8)
  340. #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
  341. #define MXC_CCM_CLPCR_SBYOS (1 << 6)
  342. #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
  343. #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
  344. #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
  345. #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
  346. #define MXC_CCM_CLPCR_LPM_MASK 0x3
  347. #define MXC_CCM_CLPCR_LPM_OFFSET 0
  348. /* Define the bits in register CISR */
  349. #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
  350. #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
  351. #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
  352. #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
  353. #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
  354. #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
  355. #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
  356. #define MXC_CCM_CISR_COSC_READY (1 << 6)
  357. #define MXC_CCM_CISR_LRF_PLL 1
  358. /* Define the bits in register CIMR */
  359. #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
  360. #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
  361. #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
  362. #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
  363. #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
  364. #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
  365. #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
  366. #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
  367. #define MXC_CCM_CIMR_MASK_LRF_PLL 1
  368. /* Define the bits in register CCOSR */
  369. #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
  370. #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
  371. #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
  372. #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
  373. #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
  374. #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
  375. #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
  376. #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
  377. #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
  378. #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
  379. /* Define the bits in registers CGPR */
  380. #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
  381. #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
  382. #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
  383. /* Define the bits in registers CCGRx */
  384. #define MXC_CCM_CCGR_CG_MASK 3
  385. #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
  386. #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
  387. #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
  388. #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
  389. #define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4
  390. #define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA)
  391. #define MXC_CCM_CCGR0_ASRC_OFFSET 6
  392. #define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET)
  393. #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
  394. #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
  395. #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
  396. #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
  397. #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
  398. #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
  399. #define MXC_CCM_CCGR0_CAN1_OFFSET 14
  400. #define MXC_CCM_CCGR0_CAN1_MASK (3<<MXC_CCM_CCGR0_CAN1_OFFSET)
  401. #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
  402. #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
  403. #define MXC_CCM_CCGR0_CAN2_OFFSET 18
  404. #define MXC_CCM_CCGR0_CAN2_MASK (3<<MXC_CCM_CCGR0_CAN2_OFFSET)
  405. #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
  406. #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
  407. #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
  408. #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
  409. #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
  410. #define MXC_CCM_CCGR0_DCIC1_MASK (3<<MXC_CCM_CCGR0_DCIC1_OFFSET)
  411. #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
  412. #define MXC_CCM_CCGR0_DCIC2_MASK (3<<MXC_CCM_CCGR0_DCIC2_OFFSET)
  413. #define MXC_CCM_CCGR0_DTCP_OFFSET 28
  414. #define MXC_CCM_CCGR0_DTCP_MASK (3<<MXC_CCM_CCGR0_DTCP_OFFSET)
  415. #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
  416. #define MXC_CCM_CCGR1_ECSPI1S_MASK (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET)
  417. #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
  418. #define MXC_CCM_CCGR1_ECSPI2S_MASK (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET)
  419. #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
  420. #define MXC_CCM_CCGR1_ECSPI3S_MASK (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET)
  421. #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
  422. #define MXC_CCM_CCGR1_ECSPI4S_MASK (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET)
  423. #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
  424. #define MXC_CCM_CCGR1_ECSPI5S_MASK (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET)
  425. #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
  426. #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
  427. #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
  428. #define MXC_CCM_CCGR1_EPIT1S_MASK (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET)
  429. #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
  430. #define MXC_CCM_CCGR1_EPIT2S_MASK (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET)
  431. #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
  432. #define MXC_CCM_CCGR1_ESAIS_MASK (3<<MXC_CCM_CCGR1_ESAIS_OFFSET)
  433. #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
  434. #define MXC_CCM_CCGR1_GPT_BUS_MASK (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET)
  435. #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
  436. #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
  437. #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
  438. #define MXC_CCM_CCGR1_GPU2D_MASK (3<<MXC_CCM_CCGR1_GPU2D_OFFSET)
  439. #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
  440. #define MXC_CCM_CCGR1_GPU3D_MASK (3<<MXC_CCM_CCGR1_GPU3D_OFFSET)
  441. #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
  442. #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
  443. #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
  444. #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
  445. #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
  446. #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
  447. #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
  448. #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
  449. #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
  450. #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
  451. #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
  452. #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
  453. #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
  454. #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
  455. #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
  456. #define MXC_CCM_CCGR2_IPMUX1_MASK (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET)
  457. #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
  458. #define MXC_CCM_CCGR2_IPMUX2_MASK (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET)
  459. #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
  460. #define MXC_CCM_CCGR2_IPMUX3_MASK (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET)
  461. #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
  462. #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
  463. #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
  464. #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
  465. #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
  466. #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
  467. #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
  468. #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
  469. #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
  470. #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
  471. #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
  472. #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
  473. #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
  474. #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
  475. #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
  476. #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
  477. #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
  478. #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
  479. #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
  480. #define MXC_CCM_CCGR3_LDB_DI0_MASK (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET)
  481. #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
  482. #define MXC_CCM_CCGR3_LDB_DI1_MASK (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET)
  483. #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
  484. #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
  485. #define MXC_CCM_CCGR3_MLB_OFFSET 18
  486. #define MXC_CCM_CCGR3_MLB_MASK (3<<MXC_CCM_CCGR3_MLB_OFFSET)
  487. #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
  488. #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
  489. #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
  490. #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
  491. #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
  492. #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
  493. #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
  494. #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
  495. #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
  496. #define MXC_CCM_CCGR3_OCRAM_MASK (3<<MXC_CCM_CCGR3_OCRAM_OFFSET)
  497. #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
  498. #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
  499. #define MXC_CCM_CCGR4_PCIE_OFFSET 0
  500. #define MXC_CCM_CCGR4_PCIE_MASK (3<<MXC_CCM_CCGR4_PCIE_OFFSET)
  501. #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
  502. #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
  503. #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
  504. #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
  505. #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
  506. #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
  507. #define MXC_CCM_CCGR4_PWM1_OFFSET 16
  508. #define MXC_CCM_CCGR4_PWM1_MASK (3<<MXC_CCM_CCGR4_PWM1_OFFSET)
  509. #define MXC_CCM_CCGR4_PWM2_OFFSET 18
  510. #define MXC_CCM_CCGR4_PWM2_MASK (3<<MXC_CCM_CCGR4_PWM2_OFFSET)
  511. #define MXC_CCM_CCGR4_PWM3_OFFSET 20
  512. #define MXC_CCM_CCGR4_PWM3_MASK (3<<MXC_CCM_CCGR4_PWM3_OFFSET)
  513. #define MXC_CCM_CCGR4_PWM4_OFFSET 22
  514. #define MXC_CCM_CCGR4_PWM4_MASK (3<<MXC_CCM_CCGR4_PWM4_OFFSET)
  515. #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
  516. #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
  517. #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
  518. #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
  519. #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
  520. #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
  521. #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
  522. #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
  523. #define MXC_CCM_CCGR5_ROM_OFFSET 0
  524. #define MXC_CCM_CCGR5_ROM_MASK (3<<MXC_CCM_CCGR5_ROM_OFFSET)
  525. #define MXC_CCM_CCGR5_SATA_OFFSET 4
  526. #define MXC_CCM_CCGR5_SATA_MASK (3<<MXC_CCM_CCGR5_SATA_OFFSET)
  527. #define MXC_CCM_CCGR5_SDMA_OFFSET 6
  528. #define MXC_CCM_CCGR5_SDMA_MASK (3<<MXC_CCM_CCGR5_SDMA_OFFSET)
  529. #define MXC_CCM_CCGR5_SPBA_OFFSET 12
  530. #define MXC_CCM_CCGR5_SPBA_MASK (3<<MXC_CCM_CCGR5_SPBA_OFFSET)
  531. #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
  532. #define MXC_CCM_CCGR5_SPDIF_MASK (3<<MXC_CCM_CCGR5_SPDIF_OFFSET)
  533. #define MXC_CCM_CCGR5_SSI1_OFFSET 18
  534. #define MXC_CCM_CCGR5_SSI1_MASK (3<<MXC_CCM_CCGR5_SSI1_OFFSET)
  535. #define MXC_CCM_CCGR5_SSI2_OFFSET 20
  536. #define MXC_CCM_CCGR5_SSI2_MASK (3<<MXC_CCM_CCGR5_SSI2_OFFSET)
  537. #define MXC_CCM_CCGR5_SSI3_OFFSET 22
  538. #define MXC_CCM_CCGR5_SSI3_MASK (3<<MXC_CCM_CCGR5_SSI3_OFFSET)
  539. #define MXC_CCM_CCGR5_UART_OFFSET 24
  540. #define MXC_CCM_CCGR5_UART_MASK (3<<MXC_CCM_CCGR5_UART_OFFSET)
  541. #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
  542. #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
  543. #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
  544. #define MXC_CCM_CCGR6_USBOH3_MASK (3<<MXC_CCM_CCGR6_USBOH3_OFFSET)
  545. #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
  546. #define MXC_CCM_CCGR6_USDHC1_MASK (3<<MXC_CCM_CCGR6_USDHC1_OFFSET)
  547. #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
  548. #define MXC_CCM_CCGR6_USDHC2_MASK (3<<MXC_CCM_CCGR6_USDHC2_OFFSET)
  549. #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
  550. #define MXC_CCM_CCGR6_USDHC3_MASK (3<<MXC_CCM_CCGR6_USDHC3_OFFSET)
  551. #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
  552. #define MXC_CCM_CCGR6_USDHC4_MASK (3<<MXC_CCM_CCGR6_USDHC4_OFFSET)
  553. #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
  554. #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
  555. #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
  556. #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
  557. #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
  558. #define BP_ANADIG_PLL_SYS_RSVD0 20
  559. #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
  560. #define BF_ANADIG_PLL_SYS_RSVD0(v) \
  561. (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
  562. #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
  563. #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
  564. #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
  565. #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
  566. #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
  567. #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
  568. #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
  569. (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
  570. #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
  571. #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
  572. #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
  573. #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
  574. #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
  575. #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
  576. #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
  577. #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
  578. #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
  579. #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
  580. #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
  581. #define BP_ANADIG_PLL_SYS_DIV_SELECT 0
  582. #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
  583. #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
  584. (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
  585. #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
  586. #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
  587. #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
  588. #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
  589. (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
  590. #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
  591. #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
  592. #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
  593. #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
  594. (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
  595. #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
  596. #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
  597. #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
  598. #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
  599. #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
  600. #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
  601. #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
  602. #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
  603. #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
  604. #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
  605. #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
  606. #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
  607. #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
  608. #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
  609. #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
  610. #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
  611. (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
  612. #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
  613. #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
  614. #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
  615. (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
  616. #define BM_ANADIG_PLL_528_LOCK 0x80000000
  617. #define BP_ANADIG_PLL_528_RSVD1 19
  618. #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
  619. #define BF_ANADIG_PLL_528_RSVD1(v) \
  620. (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
  621. #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
  622. #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
  623. #define BM_ANADIG_PLL_528_BYPASS 0x00010000
  624. #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
  625. #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
  626. #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
  627. (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
  628. #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
  629. #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
  630. #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
  631. #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
  632. #define BM_ANADIG_PLL_528_ENABLE 0x00002000
  633. #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
  634. #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
  635. #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
  636. #define BM_ANADIG_PLL_528_HALF_CP 0x00000200
  637. #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
  638. #define BM_ANADIG_PLL_528_HALF_LF 0x00000080
  639. #define BP_ANADIG_PLL_528_RSVD0 1
  640. #define BM_ANADIG_PLL_528_RSVD0 0x0000007E
  641. #define BF_ANADIG_PLL_528_RSVD0(v) \
  642. (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
  643. #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
  644. #define BP_ANADIG_PLL_528_SS_STOP 16
  645. #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
  646. #define BF_ANADIG_PLL_528_SS_STOP(v) \
  647. (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
  648. #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
  649. #define BP_ANADIG_PLL_528_SS_STEP 0
  650. #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
  651. #define BF_ANADIG_PLL_528_SS_STEP(v) \
  652. (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
  653. #define BP_ANADIG_PLL_528_NUM_RSVD0 30
  654. #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
  655. #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
  656. (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
  657. #define BP_ANADIG_PLL_528_NUM_A 0
  658. #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
  659. #define BF_ANADIG_PLL_528_NUM_A(v) \
  660. (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
  661. #define BP_ANADIG_PLL_528_DENOM_RSVD0 30
  662. #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
  663. #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
  664. (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
  665. #define BP_ANADIG_PLL_528_DENOM_B 0
  666. #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
  667. #define BF_ANADIG_PLL_528_DENOM_B(v) \
  668. (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
  669. #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
  670. #define BP_ANADIG_PLL_AUDIO_RSVD0 22
  671. #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
  672. #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
  673. (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
  674. #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
  675. #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
  676. #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
  677. #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
  678. (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
  679. #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
  680. #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
  681. #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
  682. #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
  683. #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
  684. #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
  685. (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
  686. #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
  687. #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
  688. #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
  689. #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
  690. #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
  691. #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
  692. #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
  693. #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
  694. #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
  695. #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
  696. #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
  697. #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
  698. #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
  699. #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
  700. (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
  701. #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
  702. #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
  703. #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
  704. (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
  705. #define BP_ANADIG_PLL_AUDIO_NUM_A 0
  706. #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
  707. #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
  708. (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
  709. #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
  710. #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
  711. #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
  712. (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
  713. #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
  714. #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
  715. #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
  716. (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
  717. #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
  718. #define BP_ANADIG_PLL_VIDEO_RSVD0 22
  719. #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
  720. #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
  721. (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
  722. #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
  723. #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
  724. #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
  725. #define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
  726. (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
  727. #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
  728. #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
  729. #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
  730. #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
  731. #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
  732. #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
  733. (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
  734. #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
  735. #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
  736. #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
  737. #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
  738. #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
  739. #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
  740. #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
  741. #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
  742. #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
  743. #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
  744. #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
  745. #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
  746. #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
  747. #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
  748. (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
  749. #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
  750. #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
  751. #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
  752. (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
  753. #define BP_ANADIG_PLL_VIDEO_NUM_A 0
  754. #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
  755. #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
  756. (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
  757. #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
  758. #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
  759. #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
  760. (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
  761. #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
  762. #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
  763. #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
  764. (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
  765. #define BM_ANADIG_PLL_ENET_LOCK 0x80000000
  766. #define BP_ANADIG_PLL_ENET_RSVD1 21
  767. #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
  768. #define BF_ANADIG_PLL_ENET_RSVD1(v) \
  769. (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
  770. #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
  771. #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
  772. #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
  773. #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
  774. #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
  775. #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
  776. #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
  777. #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
  778. (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
  779. #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
  780. #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
  781. #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
  782. #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
  783. #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
  784. #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
  785. #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
  786. #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
  787. #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
  788. #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
  789. #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
  790. #define BP_ANADIG_PLL_ENET_RSVD0 2
  791. #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
  792. #define BF_ANADIG_PLL_ENET_RSVD0(v) \
  793. (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
  794. #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
  795. #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
  796. #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
  797. (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
  798. #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
  799. #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
  800. #define BP_ANADIG_PFD_480_PFD3_FRAC 24
  801. #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
  802. #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
  803. (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
  804. #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
  805. #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
  806. #define BP_ANADIG_PFD_480_PFD2_FRAC 16
  807. #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
  808. #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
  809. (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
  810. #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
  811. #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
  812. #define BP_ANADIG_PFD_480_PFD1_FRAC 8
  813. #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
  814. #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
  815. (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
  816. #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
  817. #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
  818. #define BP_ANADIG_PFD_480_PFD0_FRAC 0
  819. #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
  820. #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
  821. (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
  822. #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
  823. #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
  824. #define BP_ANADIG_PFD_528_PFD3_FRAC 24
  825. #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
  826. #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
  827. (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
  828. #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
  829. #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
  830. #define BP_ANADIG_PFD_528_PFD2_FRAC 16
  831. #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
  832. #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
  833. (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
  834. #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
  835. #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
  836. #define BP_ANADIG_PFD_528_PFD1_FRAC 8
  837. #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
  838. #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
  839. (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
  840. #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
  841. #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
  842. #define BP_ANADIG_PFD_528_PFD0_FRAC 0
  843. #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
  844. #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
  845. (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
  846. #define PLL2_PFD0_FREQ 352000000
  847. #define PLL2_PFD1_FREQ 594000000
  848. #define PLL2_PFD2_FREQ 400000000
  849. #define PLL2_PFD2_DIV_FREQ 200000000
  850. #define PLL3_PFD0_FREQ 720000000
  851. #define PLL3_PFD1_FREQ 540000000
  852. #define PLL3_PFD2_FREQ 508200000
  853. #define PLL3_PFD3_FREQ 454700000
  854. #define PLL3_80M 80000000
  855. #define PLL3_60M 60000000
  856. #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */