tegra30.dtsi 5.0 KB

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  1. #include "skeleton.dtsi"
  2. / {
  3. compatible = "nvidia,tegra30";
  4. tegra_car: clock {
  5. compatible = "nvidia,tegra30-car";
  6. reg = <0x60006000 0x1000>;
  7. #clock-cells = <1>;
  8. };
  9. apbdma: dma {
  10. compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
  11. reg = <0x6000a000 0x1400>;
  12. interrupts = <0 104 0x04
  13. 0 105 0x04
  14. 0 106 0x04
  15. 0 107 0x04
  16. 0 108 0x04
  17. 0 109 0x04
  18. 0 110 0x04
  19. 0 111 0x04
  20. 0 112 0x04
  21. 0 113 0x04
  22. 0 114 0x04
  23. 0 115 0x04
  24. 0 116 0x04
  25. 0 117 0x04
  26. 0 118 0x04
  27. 0 119 0x04
  28. 0 128 0x04
  29. 0 129 0x04
  30. 0 130 0x04
  31. 0 131 0x04
  32. 0 132 0x04
  33. 0 133 0x04
  34. 0 134 0x04
  35. 0 135 0x04
  36. 0 136 0x04
  37. 0 137 0x04
  38. 0 138 0x04
  39. 0 139 0x04
  40. 0 140 0x04
  41. 0 141 0x04
  42. 0 142 0x04
  43. 0 143 0x04>;
  44. clocks = <&tegra_car 34>;
  45. };
  46. gpio: gpio {
  47. compatible = "nvidia,tegra30-gpio";
  48. reg = <0x6000d000 0x1000>;
  49. interrupts = <0 32 0x04
  50. 0 33 0x04
  51. 0 34 0x04
  52. 0 35 0x04
  53. 0 55 0x04
  54. 0 87 0x04
  55. 0 89 0x04
  56. 0 125 0x04>;
  57. #gpio-cells = <2>;
  58. gpio-controller;
  59. #interrupt-cells = <2>;
  60. interrupt-controller;
  61. };
  62. i2c@7000c000 {
  63. compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
  64. reg = <0x7000c000 0x100>;
  65. interrupts = <0 38 0x04>;
  66. #address-cells = <1>;
  67. #size-cells = <0>;
  68. clocks = <&tegra_car 12>, <&tegra_car 182>;
  69. clock-names = "div-clk", "fast-clk";
  70. status = "disabled";
  71. };
  72. i2c@7000c400 {
  73. compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
  74. reg = <0x7000c400 0x100>;
  75. interrupts = <0 84 0x04>;
  76. #address-cells = <1>;
  77. #size-cells = <0>;
  78. clocks = <&tegra_car 54>, <&tegra_car 182>;
  79. clock-names = "div-clk", "fast-clk";
  80. status = "disabled";
  81. };
  82. i2c@7000c500 {
  83. compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
  84. reg = <0x7000c500 0x100>;
  85. interrupts = <0 92 0x04>;
  86. #address-cells = <1>;
  87. #size-cells = <0>;
  88. clocks = <&tegra_car 67>, <&tegra_car 182>;
  89. clock-names = "div-clk", "fast-clk";
  90. status = "disabled";
  91. };
  92. i2c@7000c700 {
  93. compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
  94. reg = <0x7000c700 0x100>;
  95. interrupts = <0 120 0x04>;
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. clocks = <&tegra_car 103>, <&tegra_car 182>;
  99. clock-names = "div-clk", "fast-clk";
  100. status = "disabled";
  101. };
  102. i2c@7000d000 {
  103. compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
  104. reg = <0x7000d000 0x100>;
  105. interrupts = <0 53 0x04>;
  106. #address-cells = <1>;
  107. #size-cells = <0>;
  108. clocks = <&tegra_car 47>, <&tegra_car 182>;
  109. clock-names = "div-clk", "fast-clk";
  110. status = "disabled";
  111. };
  112. spi@7000d400 {
  113. compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
  114. reg = <0x7000d400 0x200>;
  115. interrupts = <0 59 0x04>;
  116. nvidia,dma-request-selector = <&apbdma 15>;
  117. #address-cells = <1>;
  118. #size-cells = <0>;
  119. clocks = <&tegra_car 41>;
  120. status = "disabled";
  121. };
  122. spi@7000d600 {
  123. compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
  124. reg = <0x7000d600 0x200>;
  125. interrupts = <0 82 0x04>;
  126. nvidia,dma-request-selector = <&apbdma 16>;
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. clocks = <&tegra_car 44>;
  130. status = "disabled";
  131. };
  132. spi@7000d800 {
  133. compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
  134. reg = <0x7000d480 0x200>;
  135. interrupts = <0 83 0x04>;
  136. nvidia,dma-request-selector = <&apbdma 17>;
  137. #address-cells = <1>;
  138. #size-cells = <0>;
  139. clocks = <&tegra_car 46>;
  140. status = "disabled";
  141. };
  142. spi@7000da00 {
  143. compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
  144. reg = <0x7000da00 0x200>;
  145. interrupts = <0 93 0x04>;
  146. nvidia,dma-request-selector = <&apbdma 18>;
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. clocks = <&tegra_car 68>;
  150. status = "disabled";
  151. };
  152. spi@7000dc00 {
  153. compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
  154. reg = <0x7000dc00 0x200>;
  155. interrupts = <0 94 0x04>;
  156. nvidia,dma-request-selector = <&apbdma 27>;
  157. #address-cells = <1>;
  158. #size-cells = <0>;
  159. clocks = <&tegra_car 104>;
  160. status = "disabled";
  161. };
  162. spi@7000de00 {
  163. compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
  164. reg = <0x7000de00 0x200>;
  165. interrupts = <0 79 0x04>;
  166. nvidia,dma-request-selector = <&apbdma 28>;
  167. #address-cells = <1>;
  168. #size-cells = <0>;
  169. clocks = <&tegra_car 105>;
  170. status = "disabled";
  171. };
  172. sdhci@78000000 {
  173. compatible = "nvidia,tegra30-sdhci";
  174. reg = <0x78000000 0x200>;
  175. interrupts = <0 14 0x04>;
  176. clocks = <&tegra_car 14>;
  177. status = "disabled";
  178. };
  179. sdhci@78000200 {
  180. compatible = "nvidia,tegra30-sdhci";
  181. reg = <0x78000200 0x200>;
  182. interrupts = <0 15 0x04>;
  183. clocks = <&tegra_car 9>;
  184. status = "disabled";
  185. };
  186. sdhci@78000400 {
  187. compatible = "nvidia,tegra30-sdhci";
  188. reg = <0x78000400 0x200>;
  189. interrupts = <0 19 0x04>;
  190. clocks = <&tegra_car 69>;
  191. status = "disabled";
  192. };
  193. sdhci@78000600 {
  194. compatible = "nvidia,tegra30-sdhci";
  195. reg = <0x78000600 0x200>;
  196. interrupts = <0 31 0x04>;
  197. clocks = <&tegra_car 15>;
  198. status = "disabled";
  199. };
  200. };