pinmux.c 25 KB

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  1. /*
  2. * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. /* Tegra30 pin multiplexing functions */
  17. #include <common.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/tegra.h>
  20. #include <asm/arch/pinmux.h>
  21. struct tegra_pingroup_desc {
  22. const char *name;
  23. enum pmux_func funcs[4];
  24. enum pmux_func func_safe;
  25. enum pmux_vddio vddio;
  26. enum pmux_pin_io io;
  27. };
  28. #define PMUX_MUXCTL_SHIFT 0
  29. #define PMUX_PULL_SHIFT 2
  30. #define PMUX_TRISTATE_SHIFT 4
  31. #define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
  32. #define PMUX_IO_SHIFT 5
  33. #define PMUX_OD_SHIFT 6
  34. #define PMUX_LOCK_SHIFT 7
  35. #define PMUX_IO_RESET_SHIFT 8
  36. #define PGRP_HSM_SHIFT 2
  37. #define PGRP_SCHMT_SHIFT 3
  38. #define PGRP_LPMD_SHIFT 4
  39. #define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
  40. #define PGRP_DRVDN_SHIFT 12
  41. #define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
  42. #define PGRP_DRVUP_SHIFT 20
  43. #define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
  44. #define PGRP_SLWR_SHIFT 28
  45. #define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
  46. #define PGRP_SLWF_SHIFT 30
  47. #define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
  48. /* Convenient macro for defining pin group properties */
  49. #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
  50. { \
  51. .vddio = PMUX_VDDIO_ ## vdd, \
  52. .funcs = { \
  53. PMUX_FUNC_ ## f0, \
  54. PMUX_FUNC_ ## f1, \
  55. PMUX_FUNC_ ## f2, \
  56. PMUX_FUNC_ ## f3, \
  57. }, \
  58. .func_safe = PMUX_FUNC_RSVD1, \
  59. .io = PMUX_PIN_ ## iod, \
  60. }
  61. /* Input and output pins */
  62. #define PINI(pg_name, vdd, f0, f1, f2, f3) \
  63. PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
  64. #define PINO(pg_name, vdd, f0, f1, f2, f3) \
  65. PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
  66. const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
  67. /* NAME VDD f0 f1 f2 f3 */
  68. PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
  69. PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
  70. PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
  71. PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
  72. PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
  73. PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
  74. PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
  75. PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
  76. PINI(ULPI_CLK, BB, SPI1, RSVD2, UARTD, ULPI),
  77. PINI(ULPI_DIR, BB, SPI1, RSVD2, UARTD, ULPI),
  78. PINI(ULPI_NXT, BB, SPI1, RSVD2, UARTD, ULPI),
  79. PINI(ULPI_STP, BB, SPI1, RSVD2, UARTD, ULPI),
  80. PINI(DAP3_FS, BB, I2S2, RSVD2, DISPA, DISPB),
  81. PINI(DAP3_DIN, BB, I2S2, RSVD2, DISPA, DISPB),
  82. PINI(DAP3_DOUT, BB, I2S2, RSVD2, DISPA, DISPB),
  83. PINI(DAP3_SCLK, BB, I2S2, RSVD2, DISPA, DISPB),
  84. PINI(GPIO_PV0, BB, RSVD1, RSVD2, RSVD3, RSVD4),
  85. PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
  86. PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
  87. PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
  88. PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
  89. PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
  90. PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
  91. PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
  92. PINI(GPIO_PV2, SDMMC1, OWR, RSVD2, RSVD3, RSVD4),
  93. PINI(GPIO_PV3, SDMMC1, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
  94. PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
  95. PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
  96. PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD3, RSVD4),
  97. PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, HDCP),
  98. PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD4),
  99. PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, HDCP),
  100. PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, HDCP),
  101. PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD4),
  102. PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD3, RSVD4),
  103. PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, HDCP),
  104. PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, HDCP),
  105. PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD3, RSVD4),
  106. PINO(LCD_DE, LCD, DISPA, DISPB, RSVD3, RSVD4),
  107. PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
  108. PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
  109. PINO(LCD_D0, LCD, DISPA, DISPB, RSVD3, RSVD4),
  110. PINO(LCD_D1, LCD, DISPA, DISPB, RSVD3, RSVD4),
  111. PINO(LCD_D2, LCD, DISPA, DISPB, RSVD3, RSVD4),
  112. PINO(LCD_D3, LCD, DISPA, DISPB, RSVD3, RSVD4),
  113. PINO(LCD_D4, LCD, DISPA, DISPB, RSVD3, RSVD4),
  114. PINO(LCD_D5, LCD, DISPA, DISPB, RSVD3, RSVD4),
  115. PINO(LCD_D6, LCD, DISPA, DISPB, RSVD3, RSVD4),
  116. PINO(LCD_D7, LCD, DISPA, DISPB, RSVD3, RSVD4),
  117. PINO(LCD_D8, LCD, DISPA, DISPB, RSVD3, RSVD4),
  118. PINO(LCD_D9, LCD, DISPA, DISPB, RSVD3, RSVD4),
  119. PINO(LCD_D10, LCD, DISPA, DISPB, RSVD3, RSVD4),
  120. PINO(LCD_D11, LCD, DISPA, DISPB, RSVD3, RSVD4),
  121. PINO(LCD_D12, LCD, DISPA, DISPB, RSVD3, RSVD4),
  122. PINO(LCD_D13, LCD, DISPA, DISPB, RSVD3, RSVD4),
  123. PINO(LCD_D14, LCD, DISPA, DISPB, RSVD3, RSVD4),
  124. PINO(LCD_D15, LCD, DISPA, DISPB, RSVD3, RSVD4),
  125. PINO(LCD_D16, LCD, DISPA, DISPB, RSVD3, RSVD4),
  126. PINO(LCD_D17, LCD, DISPA, DISPB, RSVD3, RSVD4),
  127. PINO(LCD_D18, LCD, DISPA, DISPB, RSVD3, RSVD4),
  128. PINO(LCD_D19, LCD, DISPA, DISPB, RSVD3, RSVD4),
  129. PINO(LCD_D20, LCD, DISPA, DISPB, RSVD3, RSVD4),
  130. PINO(LCD_D21, LCD, DISPA, DISPB, RSVD3, RSVD4),
  131. PINO(LCD_D22, LCD, DISPA, DISPB, RSVD3, RSVD4),
  132. PINO(LCD_D23, LCD, DISPA, DISPB, RSVD3, RSVD4),
  133. PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD4),
  134. PINO(LCD_M1, LCD, DISPA, DISPB, RSVD3, RSVD4),
  135. PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD3, RSVD4),
  136. PINI(HDMI_INT, LCD, HDMI, RSVD2, RSVD3, RSVD4),
  137. PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
  138. PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
  139. PINI(CRT_HSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
  140. PINI(CRT_VSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
  141. PINI(VI_D0, VI, DDR, RSVD2, VI, RSVD4),
  142. PINI(VI_D1, VI, DDR, SDMMC2, VI, RSVD4),
  143. PINI(VI_D2, VI, DDR, SDMMC2, VI, RSVD4),
  144. PINI(VI_D3, VI, DDR, SDMMC2, VI, RSVD4),
  145. PINI(VI_D4, VI, DDR, SDMMC2, VI, RSVD4),
  146. PINI(VI_D5, VI, DDR, SDMMC2, VI, RSVD4),
  147. PINI(VI_D6, VI, DDR, SDMMC2, VI, RSVD4),
  148. PINI(VI_D7, VI, DDR, SDMMC2, VI, RSVD4),
  149. PINI(VI_D8, VI, DDR, SDMMC2, VI, RSVD4),
  150. PINI(VI_D9, VI, DDR, SDMMC2, VI, RSVD4),
  151. PINI(VI_D10, VI, DDR, RSVD2, VI, RSVD4),
  152. PINI(VI_D11, VI, DDR, RSVD2, VI, RSVD4),
  153. PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD4),
  154. PINI(VI_MCLK, VI, VI, VI, VI, VI),
  155. PINI(VI_VSYNC, VI, DDR, RSVD2, VI, RSVD4),
  156. PINI(VI_HSYNC, VI, DDR, RSVD2, VI, RSVD4),
  157. PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
  158. PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
  159. PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4),
  160. PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4),
  161. PINI(UART3_TXD, UART, UARTC, RSVD2, GMI, RSVD4),
  162. PINI(UART3_RXD, UART, UARTC, RSVD2, GMI, RSVD4),
  163. PINI(UART3_CTS_N, UART, UARTC, RSVD2, GMI, RSVD4),
  164. PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD4),
  165. PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD4),
  166. PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD4),
  167. PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD4),
  168. PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD4),
  169. PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD4),
  170. PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD4),
  171. PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD4),
  172. PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
  173. PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
  174. PINI(DAP4_FS, UART, I2S3, RSVD2, GMI, RSVD4),
  175. PINI(DAP4_DIN, UART, I2S3, RSVD2, GMI, RSVD4),
  176. PINI(DAP4_DOUT, UART, I2S3, RSVD2, GMI, RSVD4),
  177. PINI(DAP4_SCLK, UART, I2S3, RSVD2, GMI, RSVD4),
  178. PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
  179. PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
  180. PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
  181. PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD4),
  182. PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD4),
  183. PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD4),
  184. PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD4),
  185. PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, DTV),
  186. PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV),
  187. PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD4),
  188. PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
  189. PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD4),
  190. PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA),
  191. PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT),
  192. PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
  193. PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
  194. PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
  195. PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
  196. PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
  197. PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD4),
  198. PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD4),
  199. PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD4),
  200. PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD4),
  201. PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD4),
  202. PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD4),
  203. PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD4),
  204. PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD4),
  205. PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD4),
  206. PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD4),
  207. PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD4),
  208. PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT),
  209. PINI(GMI_A17, GMI, UARTD, SPI4, GMI, DTV),
  210. PINI(GMI_A18, GMI, UARTD, SPI4, GMI, DTV),
  211. PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD4),
  212. PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD4),
  213. PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD4),
  214. PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD4),
  215. PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
  216. PINI(GEN2_I2C_SCL, GMI, I2C2, HDCP, GMI, RSVD4),
  217. PINI(GEN2_I2C_SDA, GMI, I2C2, HDCP, GMI, RSVD4),
  218. PINI(SDMMC4_CLK, SDMMC4, RSVD1, NAND, GMI, SDMMC4),
  219. PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4),
  220. PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
  221. PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
  222. PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
  223. PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
  224. PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4),
  225. PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4),
  226. PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4),
  227. PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4),
  228. PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD2, RSVD3, SDMMC4),
  229. PINI(CAM_MCLK, CAM, VI, RSVD2, VI_ALT2, SDMMC4),
  230. PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
  231. PINI(GPIO_PBB0, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
  232. PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, SDMMC4),
  233. PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, SDMMC4),
  234. PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, SDMMC4),
  235. PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, SDMMC4),
  236. PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, SDMMC4),
  237. PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, SDMMC4),
  238. PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
  239. PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
  240. PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
  241. PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
  242. PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
  243. PINI(KB_ROW0, SYS, KBC, NAND, RSVD3, RSVD4),
  244. PINI(KB_ROW1, SYS, KBC, NAND, RSVD3, RSVD4),
  245. PINI(KB_ROW2, SYS, KBC, NAND, RSVD3, RSVD4),
  246. PINI(KB_ROW3, SYS, KBC, NAND, RSVD3, RSVD4),
  247. PINI(KB_ROW4, SYS, KBC, NAND, TRACE, RSVD4),
  248. PINI(KB_ROW5, SYS, KBC, NAND, TRACE, OWR),
  249. PINI(KB_ROW6, SYS, KBC, NAND, SDMMC2, MIO),
  250. PINI(KB_ROW7, SYS, KBC, NAND, SDMMC2, MIO),
  251. PINI(KB_ROW8, SYS, KBC, NAND, SDMMC2, MIO),
  252. PINI(KB_ROW9, SYS, KBC, NAND, SDMMC2, MIO),
  253. PINI(KB_ROW10, SYS, KBC, NAND, SDMMC2, MIO),
  254. PINI(KB_ROW11, SYS, KBC, NAND, SDMMC2, MIO),
  255. PINI(KB_ROW12, SYS, KBC, NAND, SDMMC2, MIO),
  256. PINI(KB_ROW13, SYS, KBC, NAND, SDMMC2, MIO),
  257. PINI(KB_ROW14, SYS, KBC, NAND, SDMMC2, MIO),
  258. PINI(KB_ROW15, SYS, KBC, NAND, SDMMC2, MIO),
  259. PINI(KB_COL0, SYS, KBC, NAND, TRACE, TEST),
  260. PINI(KB_COL1, SYS, KBC, NAND, TRACE, TEST),
  261. PINI(KB_COL2, SYS, KBC, NAND, TRACE, RSVD4),
  262. PINI(KB_COL3, SYS, KBC, NAND, TRACE, RSVD4),
  263. PINI(KB_COL4, SYS, KBC, NAND, TRACE, RSVD4),
  264. PINI(KB_COL5, SYS, KBC, NAND, TRACE, RSVD4),
  265. PINI(KB_COL6, SYS, KBC, NAND, TRACE, MIO),
  266. PINI(KB_COL7, SYS, KBC, NAND, TRACE, MIO),
  267. PINI(CLK_32K_OUT, SYS, BLINK, RSVD2, RSVD3, RSVD4),
  268. PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
  269. PINI(CORE_PWR_REQ, SYS, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
  270. PINI(CPU_PWR_REQ, SYS, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
  271. PINI(PWR_INT_N, SYS, PWR_INT_N, RSVD2, RSVD3, RSVD4),
  272. PINI(CLK_32K_IN, SYS, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
  273. PINI(OWR, SYS, OWR, CEC, RSVD3, RSVD4),
  274. PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2),
  275. PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2),
  276. PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2),
  277. PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2),
  278. PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD3, RSVD4),
  279. PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
  280. PINI(SPDIF_IN, AUDIO, SPDIF, HDA, I2C1, SDMMC2),
  281. PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, I2C1, SDMMC2),
  282. PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, GMI),
  283. PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, GMI),
  284. PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, GMI),
  285. PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, GMI),
  286. PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, GMI, GMI),
  287. PINI(SPI2_MISO, AUDIO, SPI6, SPI2, GMI, GMI),
  288. PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, GMI, GMI),
  289. PINI(SPI2_SCK, AUDIO, SPI6, SPI2, GMI, GMI),
  290. PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
  291. PINI(SPI1_SCK, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
  292. PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
  293. PINI(SPI1_MISO, AUDIO, SPI3, SPI1, SPI2_ALT, RSVD4),
  294. PINI(SPI2_CS1_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
  295. PINI(SPI2_CS2_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
  296. PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, SPI3),
  297. PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, SPI2),
  298. PINI(SDMMC3_DAT0, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
  299. PINI(SDMMC3_DAT1, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
  300. PINI(SDMMC3_DAT2, SDMMC3, RSVD1, PWM1, SDMMC3, SPI3),
  301. PINI(SDMMC3_DAT3, SDMMC3, RSVD1, PWM0, SDMMC3, SPI3),
  302. PINI(SDMMC3_DAT4, SDMMC3, PWM1, SPI4, SDMMC3, SPI2),
  303. PINI(SDMMC3_DAT5, SDMMC3, PWM0, SPI4, SDMMC3, SPI2),
  304. PINI(SDMMC3_DAT6, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
  305. PINI(SDMMC3_DAT7, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
  306. PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
  307. PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
  308. PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
  309. PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
  310. PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
  311. PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
  312. PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
  313. PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
  314. PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
  315. PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
  316. PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
  317. };
  318. void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
  319. {
  320. struct pmux_tri_ctlr *pmt =
  321. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  322. u32 *tri = &pmt->pmt_ctl[pin];
  323. u32 reg;
  324. /* Error check on pin */
  325. assert(pmux_pingrp_isvalid(pin));
  326. reg = readl(tri);
  327. if (enable)
  328. reg |= PMUX_TRISTATE_MASK;
  329. else
  330. reg &= ~PMUX_TRISTATE_MASK;
  331. writel(reg, tri);
  332. }
  333. void pinmux_tristate_enable(enum pmux_pingrp pin)
  334. {
  335. pinmux_set_tristate(pin, 1);
  336. }
  337. void pinmux_tristate_disable(enum pmux_pingrp pin)
  338. {
  339. pinmux_set_tristate(pin, 0);
  340. }
  341. void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
  342. {
  343. struct pmux_tri_ctlr *pmt =
  344. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  345. u32 *pull = &pmt->pmt_ctl[pin];
  346. u32 reg;
  347. /* Error check on pin and pupd */
  348. assert(pmux_pingrp_isvalid(pin));
  349. assert(pmux_pin_pupd_isvalid(pupd));
  350. reg = readl(pull);
  351. reg &= ~(0x3 << PMUX_PULL_SHIFT);
  352. reg |= (pupd << PMUX_PULL_SHIFT);
  353. writel(reg, pull);
  354. }
  355. void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
  356. {
  357. struct pmux_tri_ctlr *pmt =
  358. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  359. u32 *muxctl = &pmt->pmt_ctl[pin];
  360. int i, mux = -1;
  361. u32 reg;
  362. /* Error check on pin and func */
  363. assert(pmux_pingrp_isvalid(pin));
  364. assert(pmux_func_isvalid(func));
  365. /* Handle special values */
  366. if (func == PMUX_FUNC_SAFE)
  367. func = tegra_soc_pingroups[pin].func_safe;
  368. if (func & PMUX_FUNC_RSVD1) {
  369. mux = func & 0x3;
  370. } else {
  371. /* Search for the appropriate function */
  372. for (i = 0; i < 4; i++) {
  373. if (tegra_soc_pingroups[pin].funcs[i] == func) {
  374. mux = i;
  375. break;
  376. }
  377. }
  378. }
  379. assert(mux != -1);
  380. reg = readl(muxctl);
  381. reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
  382. reg |= (mux << PMUX_MUXCTL_SHIFT);
  383. writel(reg, muxctl);
  384. }
  385. void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
  386. {
  387. struct pmux_tri_ctlr *pmt =
  388. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  389. u32 *pin_io = &pmt->pmt_ctl[pin];
  390. u32 reg;
  391. /* Error check on pin and io */
  392. assert(pmux_pingrp_isvalid(pin));
  393. assert(pmux_pin_io_isvalid(io));
  394. reg = readl(pin_io);
  395. reg &= ~(0x1 << PMUX_IO_SHIFT);
  396. reg |= (io & 0x1) << PMUX_IO_SHIFT;
  397. writel(reg, pin_io);
  398. }
  399. static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
  400. {
  401. struct pmux_tri_ctlr *pmt =
  402. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  403. u32 *pin_lock = &pmt->pmt_ctl[pin];
  404. u32 reg;
  405. /* Error check on pin and lock */
  406. assert(pmux_pingrp_isvalid(pin));
  407. assert(pmux_pin_lock_isvalid(lock));
  408. if (lock == PMUX_PIN_LOCK_DEFAULT)
  409. return 0;
  410. reg = readl(pin_lock);
  411. reg &= ~(0x1 << PMUX_LOCK_SHIFT);
  412. if (lock == PMUX_PIN_LOCK_ENABLE)
  413. reg |= (0x1 << PMUX_LOCK_SHIFT);
  414. else {
  415. /* lock == DISABLE, which isn't possible */
  416. printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
  417. __func__, lock);
  418. }
  419. writel(reg, pin_lock);
  420. return 0;
  421. }
  422. static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
  423. {
  424. struct pmux_tri_ctlr *pmt =
  425. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  426. u32 *pin_od = &pmt->pmt_ctl[pin];
  427. u32 reg;
  428. /* Error check on pin and od */
  429. assert(pmux_pingrp_isvalid(pin));
  430. assert(pmux_pin_od_isvalid(od));
  431. if (od == PMUX_PIN_OD_DEFAULT)
  432. return 0;
  433. reg = readl(pin_od);
  434. reg &= ~(0x1 << PMUX_OD_SHIFT);
  435. if (od == PMUX_PIN_OD_ENABLE)
  436. reg |= (0x1 << PMUX_OD_SHIFT);
  437. writel(reg, pin_od);
  438. return 0;
  439. }
  440. static int pinmux_set_ioreset(enum pmux_pingrp pin,
  441. enum pmux_pin_ioreset ioreset)
  442. {
  443. struct pmux_tri_ctlr *pmt =
  444. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  445. u32 *pin_ioreset = &pmt->pmt_ctl[pin];
  446. u32 reg;
  447. /* Error check on pin and ioreset */
  448. assert(pmux_pingrp_isvalid(pin));
  449. assert(pmux_pin_ioreset_isvalid(ioreset));
  450. if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
  451. return 0;
  452. reg = readl(pin_ioreset);
  453. reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
  454. if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
  455. reg |= (0x1 << PMUX_IO_RESET_SHIFT);
  456. writel(reg, pin_ioreset);
  457. return 0;
  458. }
  459. void pinmux_config_pingroup(struct pingroup_config *config)
  460. {
  461. enum pmux_pingrp pin = config->pingroup;
  462. pinmux_set_func(pin, config->func);
  463. pinmux_set_pullupdown(pin, config->pull);
  464. pinmux_set_tristate(pin, config->tristate);
  465. pinmux_set_io(pin, config->io);
  466. pinmux_set_lock(pin, config->lock);
  467. pinmux_set_od(pin, config->od);
  468. pinmux_set_ioreset(pin, config->ioreset);
  469. }
  470. void pinmux_config_table(struct pingroup_config *config, int len)
  471. {
  472. int i;
  473. for (i = 0; i < len; i++)
  474. pinmux_config_pingroup(&config[i]);
  475. }
  476. static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad,
  477. int slwf)
  478. {
  479. struct pmux_tri_ctlr *pmt =
  480. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  481. u32 *pad_slwf = &pmt->pmt_drive[pad];
  482. u32 reg;
  483. /* Error check on pad and slwf */
  484. assert(pmux_padgrp_isvalid(pad));
  485. assert(pmux_pad_slw_isvalid(slwf));
  486. /* NONE means unspecified/do not change/use POR value */
  487. if (slwf == PGRP_SLWF_NONE)
  488. return 0;
  489. reg = readl(pad_slwf);
  490. reg &= ~PGRP_SLWF_MASK;
  491. reg |= (slwf << PGRP_SLWF_SHIFT);
  492. writel(reg, pad_slwf);
  493. return 0;
  494. }
  495. static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
  496. {
  497. struct pmux_tri_ctlr *pmt =
  498. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  499. u32 *pad_slwr = &pmt->pmt_drive[pad];
  500. u32 reg;
  501. /* Error check on pad and slwr */
  502. assert(pmux_padgrp_isvalid(pad));
  503. assert(pmux_pad_slw_isvalid(slwr));
  504. /* NONE means unspecified/do not change/use POR value */
  505. if (slwr == PGRP_SLWR_NONE)
  506. return 0;
  507. reg = readl(pad_slwr);
  508. reg &= ~PGRP_SLWR_MASK;
  509. reg |= (slwr << PGRP_SLWR_SHIFT);
  510. writel(reg, pad_slwr);
  511. return 0;
  512. }
  513. static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
  514. {
  515. struct pmux_tri_ctlr *pmt =
  516. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  517. u32 *pad_drvup = &pmt->pmt_drive[pad];
  518. u32 reg;
  519. /* Error check on pad and drvup */
  520. assert(pmux_padgrp_isvalid(pad));
  521. assert(pmux_pad_drv_isvalid(drvup));
  522. /* NONE means unspecified/do not change/use POR value */
  523. if (drvup == PGRP_DRVUP_NONE)
  524. return 0;
  525. reg = readl(pad_drvup);
  526. reg &= ~PGRP_DRVUP_MASK;
  527. reg |= (drvup << PGRP_DRVUP_SHIFT);
  528. writel(reg, pad_drvup);
  529. return 0;
  530. }
  531. static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
  532. {
  533. struct pmux_tri_ctlr *pmt =
  534. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  535. u32 *pad_drvdn = &pmt->pmt_drive[pad];
  536. u32 reg;
  537. /* Error check on pad and drvdn */
  538. assert(pmux_padgrp_isvalid(pad));
  539. assert(pmux_pad_drv_isvalid(drvdn));
  540. /* NONE means unspecified/do not change/use POR value */
  541. if (drvdn == PGRP_DRVDN_NONE)
  542. return 0;
  543. reg = readl(pad_drvdn);
  544. reg &= ~PGRP_DRVDN_MASK;
  545. reg |= (drvdn << PGRP_DRVDN_SHIFT);
  546. writel(reg, pad_drvdn);
  547. return 0;
  548. }
  549. static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
  550. {
  551. struct pmux_tri_ctlr *pmt =
  552. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  553. u32 *pad_lpmd = &pmt->pmt_drive[pad];
  554. u32 reg;
  555. /* Error check pad and lpmd value */
  556. assert(pmux_padgrp_isvalid(pad));
  557. assert(pmux_pad_lpmd_isvalid(lpmd));
  558. /* NONE means unspecified/do not change/use POR value */
  559. if (lpmd == PGRP_LPMD_NONE)
  560. return 0;
  561. reg = readl(pad_lpmd);
  562. reg &= ~PGRP_LPMD_MASK;
  563. reg |= (lpmd << PGRP_LPMD_SHIFT);
  564. writel(reg, pad_lpmd);
  565. return 0;
  566. }
  567. static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
  568. {
  569. struct pmux_tri_ctlr *pmt =
  570. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  571. u32 *pad_schmt = &pmt->pmt_drive[pad];
  572. u32 reg;
  573. /* Error check pad */
  574. assert(pmux_padgrp_isvalid(pad));
  575. reg = readl(pad_schmt);
  576. reg &= ~(1 << PGRP_SCHMT_SHIFT);
  577. if (schmt == PGRP_SCHMT_ENABLE)
  578. reg |= (0x1 << PGRP_SCHMT_SHIFT);
  579. writel(reg, pad_schmt);
  580. return 0;
  581. }
  582. static int padgrp_set_hsm(enum pdrive_pingrp pad,
  583. enum pgrp_hsm hsm)
  584. {
  585. struct pmux_tri_ctlr *pmt =
  586. (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
  587. u32 *pad_hsm = &pmt->pmt_drive[pad];
  588. u32 reg;
  589. /* Error check pad */
  590. assert(pmux_padgrp_isvalid(pad));
  591. reg = readl(pad_hsm);
  592. reg &= ~(1 << PGRP_HSM_SHIFT);
  593. if (hsm == PGRP_HSM_ENABLE)
  594. reg |= (0x1 << PGRP_HSM_SHIFT);
  595. writel(reg, pad_hsm);
  596. return 0;
  597. }
  598. void padctrl_config_pingroup(struct padctrl_config *config)
  599. {
  600. enum pdrive_pingrp pad = config->padgrp;
  601. padgrp_set_drvup_slwf(pad, config->slwf);
  602. padgrp_set_drvdn_slwr(pad, config->slwr);
  603. padgrp_set_drvup(pad, config->drvup);
  604. padgrp_set_drvdn(pad, config->drvdn);
  605. padgrp_set_lpmd(pad, config->lpmd);
  606. padgrp_set_schmt(pad, config->schmt);
  607. padgrp_set_hsm(pad, config->hsm);
  608. }
  609. void padgrp_config_table(struct padctrl_config *config, int len)
  610. {
  611. int i;
  612. for (i = 0; i < len; i++)
  613. padctrl_config_pingroup(&config[i]);
  614. }