slcr.c 1.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263
  1. /*
  2. * Copyright (c) 2013 Xilinx Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/io.h>
  24. #include <malloc.h>
  25. #include <asm/arch/hardware.h>
  26. #define SLCR_LOCK_MAGIC 0x767B
  27. #define SLCR_UNLOCK_MAGIC 0xDF0D
  28. static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
  29. void zynq_slcr_lock(void)
  30. {
  31. if (!slcr_lock)
  32. writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
  33. }
  34. void zynq_slcr_unlock(void)
  35. {
  36. if (slcr_lock)
  37. writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
  38. }
  39. /* Reset the entire system */
  40. void zynq_slcr_cpu_reset(void)
  41. {
  42. /*
  43. * Unlock the SLCR then reset the system.
  44. * Note that this seems to require raw i/o
  45. * functions or there's a lockup?
  46. */
  47. zynq_slcr_unlock();
  48. /*
  49. * Clear 0x0F000000 bits of reboot status register to workaround
  50. * the FSBL not loading the bitstream after soft-reboot
  51. * This is a temporary solution until we know more.
  52. */
  53. clrbits_le32(&slcr_base->reboot_status, 0xF000000);
  54. writel(1, &slcr_base->pss_rst_ctrl);
  55. }