cpu.c 1.8 KB

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  1. /*
  2. * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
  3. * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/io.h>
  25. #include <asm/arch/sys_proto.h>
  26. #include <asm/arch/hardware.h>
  27. void lowlevel_init(void)
  28. {
  29. zynq_slcr_unlock();
  30. /* remap DDR to zero, FILTERSTART */
  31. writel(0, &scu_base->filter_start);
  32. /* Device config APB, unlock the PCAP */
  33. writel(0x757BDF0D, &devcfg_base->unlock);
  34. writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
  35. /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
  36. writel(0x1F, &slcr_base->ocm_cfg);
  37. /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
  38. writel(0x0, &slcr_base->fpga_rst_ctrl);
  39. /* TZ_DDR_RAM, Set DDR trust zone non-secure */
  40. writel(0xFFFFFFFF, &slcr_base->trust_zone);
  41. /* Set urgent bits with register */
  42. writel(0x0, &slcr_base->ddr_urgent_sel);
  43. /* Urgent write, ports S2/S3 */
  44. writel(0xC, &slcr_base->ddr_urgent);
  45. zynq_slcr_lock();
  46. }
  47. void reset_cpu(ulong addr)
  48. {
  49. zynq_slcr_cpu_reset();
  50. while (1)
  51. ;
  52. }