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  1. /*
  2. * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
  3. *
  4. * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
  5. *
  6. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  7. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  8. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  9. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  10. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  11. * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
  12. *
  13. * See file CREDITS for list of people who contributed to this
  14. * project.
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation; either version 2 of
  19. * the License, or (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29. * MA 02111-1307 USA
  30. */
  31. #include <asm-offsets.h>
  32. #include <config.h>
  33. #include <version.h>
  34. #include <asm/system.h>
  35. #include <linux/linkage.h>
  36. .globl _start
  37. _start: b reset
  38. ldr pc, _undefined_instruction
  39. ldr pc, _software_interrupt
  40. ldr pc, _prefetch_abort
  41. ldr pc, _data_abort
  42. ldr pc, _not_used
  43. ldr pc, _irq
  44. ldr pc, _fiq
  45. #ifdef CONFIG_SPL_BUILD
  46. _undefined_instruction: .word _undefined_instruction
  47. _software_interrupt: .word _software_interrupt
  48. _prefetch_abort: .word _prefetch_abort
  49. _data_abort: .word _data_abort
  50. _not_used: .word _not_used
  51. _irq: .word _irq
  52. _fiq: .word _fiq
  53. _pad: .word 0x12345678 /* now 16*4=64 */
  54. #else
  55. _undefined_instruction: .word undefined_instruction
  56. _software_interrupt: .word software_interrupt
  57. _prefetch_abort: .word prefetch_abort
  58. _data_abort: .word data_abort
  59. _not_used: .word not_used
  60. _irq: .word irq
  61. _fiq: .word fiq
  62. _pad: .word 0x12345678 /* now 16*4=64 */
  63. #endif /* CONFIG_SPL_BUILD */
  64. .global _end_vect
  65. _end_vect:
  66. .balignl 16,0xdeadbeef
  67. /*************************************************************************
  68. *
  69. * Startup Code (reset vector)
  70. *
  71. * do important init only if we don't start from memory!
  72. * setup Memory and board specific bits prior to relocation.
  73. * relocate armboot to ram
  74. * setup stack
  75. *
  76. *************************************************************************/
  77. .globl _TEXT_BASE
  78. _TEXT_BASE:
  79. .word CONFIG_SYS_TEXT_BASE
  80. /*
  81. * These are defined in the board-specific linker script.
  82. */
  83. .globl _bss_start_ofs
  84. _bss_start_ofs:
  85. .word __bss_start - _start
  86. .global _image_copy_end_ofs
  87. _image_copy_end_ofs:
  88. .word __image_copy_end - _start
  89. .globl _bss_end_ofs
  90. _bss_end_ofs:
  91. .word __bss_end - _start
  92. .globl _end_ofs
  93. _end_ofs:
  94. .word _end - _start
  95. #ifdef CONFIG_USE_IRQ
  96. /* IRQ stack memory (calculated at run-time) */
  97. .globl IRQ_STACK_START
  98. IRQ_STACK_START:
  99. .word 0x0badc0de
  100. /* IRQ stack memory (calculated at run-time) */
  101. .globl FIQ_STACK_START
  102. FIQ_STACK_START:
  103. .word 0x0badc0de
  104. #endif
  105. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  106. .globl IRQ_STACK_START_IN
  107. IRQ_STACK_START_IN:
  108. .word 0x0badc0de
  109. /*
  110. * the actual reset code
  111. */
  112. reset:
  113. bl save_boot_params
  114. /*
  115. * set the cpu to SVC32 mode
  116. */
  117. mrs r0, cpsr
  118. bic r0, r0, #0x1f
  119. orr r0, r0, #0xd3
  120. msr cpsr,r0
  121. /*
  122. * Setup vector:
  123. * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
  124. * Continue to use ROM code vector only in OMAP4 spl)
  125. */
  126. #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
  127. /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
  128. mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
  129. bic r0, #CR_V @ V = 0
  130. mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
  131. /* Set vector address in CP15 VBAR register */
  132. ldr r0, =_start
  133. mcr p15, 0, r0, c12, c0, 0 @Set VBAR
  134. #endif
  135. /* the mask ROM code should have PLL and others stable */
  136. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  137. bl cpu_init_cp15
  138. bl cpu_init_crit
  139. #endif
  140. bl _main
  141. /*------------------------------------------------------------------------------*/
  142. #ifndef CONFIG_SPL_BUILD
  143. /*
  144. * void relocate_code (addr_sp, gd, addr_moni)
  145. *
  146. * This "function" does not return, instead it continues in RAM
  147. * after relocating the monitor code.
  148. *
  149. */
  150. ENTRY(relocate_code)
  151. mov r4, r0 /* save addr_sp */
  152. mov r5, r1 /* save addr of gd */
  153. mov r6, r2 /* save addr of destination */
  154. adr r0, _start
  155. cmp r0, r6
  156. moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
  157. beq relocate_done /* skip relocation */
  158. mov r1, r6 /* r1 <- scratch for copy_loop */
  159. ldr r3, _image_copy_end_ofs
  160. add r2, r0, r3 /* r2 <- source end address */
  161. copy_loop:
  162. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  163. stmia r1!, {r9-r10} /* copy to target address [r1] */
  164. cmp r0, r2 /* until source end address [r2] */
  165. blo copy_loop
  166. /*
  167. * fix .rel.dyn relocations
  168. */
  169. ldr r0, _TEXT_BASE /* r0 <- Text base */
  170. sub r9, r6, r0 /* r9 <- relocation offset */
  171. ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
  172. add r10, r10, r0 /* r10 <- sym table in FLASH */
  173. ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
  174. add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
  175. ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
  176. add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
  177. fixloop:
  178. ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
  179. add r0, r0, r9 /* r0 <- location to fix up in RAM */
  180. ldr r1, [r2, #4]
  181. and r7, r1, #0xff
  182. cmp r7, #23 /* relative fixup? */
  183. beq fixrel
  184. cmp r7, #2 /* absolute fixup? */
  185. beq fixabs
  186. /* ignore unknown type of fixup */
  187. b fixnext
  188. fixabs:
  189. /* absolute fix: set location to (offset) symbol value */
  190. mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
  191. add r1, r10, r1 /* r1 <- address of symbol in table */
  192. ldr r1, [r1, #4] /* r1 <- symbol value */
  193. add r1, r1, r9 /* r1 <- relocated sym addr */
  194. b fixnext
  195. fixrel:
  196. /* relative fix: increase location by offset */
  197. ldr r1, [r0]
  198. add r1, r1, r9
  199. fixnext:
  200. str r1, [r0]
  201. add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
  202. cmp r2, r3
  203. blo fixloop
  204. relocate_done:
  205. bx lr
  206. _rel_dyn_start_ofs:
  207. .word __rel_dyn_start - _start
  208. _rel_dyn_end_ofs:
  209. .word __rel_dyn_end - _start
  210. _dynsym_start_ofs:
  211. .word __dynsym_start - _start
  212. ENDPROC(relocate_code)
  213. #endif
  214. ENTRY(c_runtime_cpu_setup)
  215. /*
  216. * If I-cache is enabled invalidate it
  217. */
  218. #ifndef CONFIG_SYS_ICACHE_OFF
  219. mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
  220. mcr p15, 0, r0, c7, c10, 4 @ DSB
  221. mcr p15, 0, r0, c7, c5, 4 @ ISB
  222. #endif
  223. /*
  224. * Move vector table
  225. */
  226. #if !defined(CONFIG_TEGRA)
  227. /* Set vector address in CP15 VBAR register */
  228. ldr r0, =_start
  229. add r0, r0, r9
  230. mcr p15, 0, r0, c12, c0, 0 @Set VBAR
  231. #endif /* !Tegra */
  232. bx lr
  233. ENDPROC(c_runtime_cpu_setup)
  234. /*************************************************************************
  235. *
  236. * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
  237. * __attribute__((weak));
  238. *
  239. * Stack pointer is not yet initialized at this moment
  240. * Don't save anything to stack even if compiled with -O0
  241. *
  242. *************************************************************************/
  243. ENTRY(save_boot_params)
  244. bx lr @ back to my caller
  245. ENDPROC(save_boot_params)
  246. .weak save_boot_params
  247. /*************************************************************************
  248. *
  249. * cpu_init_cp15
  250. *
  251. * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
  252. * CONFIG_SYS_ICACHE_OFF is defined.
  253. *
  254. *************************************************************************/
  255. ENTRY(cpu_init_cp15)
  256. /*
  257. * Invalidate L1 I/D
  258. */
  259. mov r0, #0 @ set up for MCR
  260. mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
  261. mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
  262. mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
  263. mcr p15, 0, r0, c7, c10, 4 @ DSB
  264. mcr p15, 0, r0, c7, c5, 4 @ ISB
  265. /*
  266. * disable MMU stuff and caches
  267. */
  268. mrc p15, 0, r0, c1, c0, 0
  269. bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
  270. bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
  271. orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
  272. orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
  273. #ifdef CONFIG_SYS_ICACHE_OFF
  274. bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
  275. #else
  276. orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
  277. #endif
  278. mcr p15, 0, r0, c1, c0, 0
  279. #ifdef CONFIG_ARM_ERRATA_742230
  280. mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
  281. orr r0, r0, #1 << 4 @ set bit #4
  282. mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
  283. #endif
  284. #ifdef CONFIG_ARM_ERRATA_743622
  285. mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
  286. orr r0, r0, #1 << 6 @ set bit #6
  287. mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
  288. #endif
  289. #ifdef CONFIG_ARM_ERRATA_751472
  290. mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
  291. orr r0, r0, #1 << 11 @ set bit #11
  292. mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
  293. #endif
  294. mov pc, lr @ back to my caller
  295. ENDPROC(cpu_init_cp15)
  296. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  297. /*************************************************************************
  298. *
  299. * CPU_init_critical registers
  300. *
  301. * setup important registers
  302. * setup memory timing
  303. *
  304. *************************************************************************/
  305. ENTRY(cpu_init_crit)
  306. /*
  307. * Jump to board specific initialization...
  308. * The Mask ROM will have already initialized
  309. * basic memory. Go here to bump up clock rate and handle
  310. * wake up conditions.
  311. */
  312. b lowlevel_init @ go setup pll,mux,memory
  313. ENDPROC(cpu_init_crit)
  314. #endif
  315. #ifndef CONFIG_SPL_BUILD
  316. /*
  317. *************************************************************************
  318. *
  319. * Interrupt handling
  320. *
  321. *************************************************************************
  322. */
  323. @
  324. @ IRQ stack frame.
  325. @
  326. #define S_FRAME_SIZE 72
  327. #define S_OLD_R0 68
  328. #define S_PSR 64
  329. #define S_PC 60
  330. #define S_LR 56
  331. #define S_SP 52
  332. #define S_IP 48
  333. #define S_FP 44
  334. #define S_R10 40
  335. #define S_R9 36
  336. #define S_R8 32
  337. #define S_R7 28
  338. #define S_R6 24
  339. #define S_R5 20
  340. #define S_R4 16
  341. #define S_R3 12
  342. #define S_R2 8
  343. #define S_R1 4
  344. #define S_R0 0
  345. #define MODE_SVC 0x13
  346. #define I_BIT 0x80
  347. /*
  348. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  349. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  350. */
  351. .macro bad_save_user_regs
  352. sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
  353. @ user stack
  354. stmia sp, {r0 - r12} @ Save user registers (now in
  355. @ svc mode) r0-r12
  356. ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
  357. @ stack
  358. ldmia r2, {r2 - r3} @ get values for "aborted" pc
  359. @ and cpsr (into parm regs)
  360. add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
  361. add r5, sp, #S_SP
  362. mov r1, lr
  363. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  364. mov r0, sp @ save current stack into r0
  365. @ (param register)
  366. .endm
  367. .macro irq_save_user_regs
  368. sub sp, sp, #S_FRAME_SIZE
  369. stmia sp, {r0 - r12} @ Calling r0-r12
  370. add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
  371. @ a reserved stack spot would
  372. @ be good.
  373. stmdb r8, {sp, lr}^ @ Calling SP, LR
  374. str lr, [r8, #0] @ Save calling PC
  375. mrs r6, spsr
  376. str r6, [r8, #4] @ Save CPSR
  377. str r0, [r8, #8] @ Save OLD_R0
  378. mov r0, sp
  379. .endm
  380. .macro irq_restore_user_regs
  381. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  382. mov r0, r0
  383. ldr lr, [sp, #S_PC] @ Get PC
  384. add sp, sp, #S_FRAME_SIZE
  385. subs pc, lr, #4 @ return & move spsr_svc into
  386. @ cpsr
  387. .endm
  388. .macro get_bad_stack
  389. ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
  390. @ in banked mode)
  391. str lr, [r13] @ save caller lr in position 0
  392. @ of saved stack
  393. mrs lr, spsr @ get the spsr
  394. str lr, [r13, #4] @ save spsr in position 1 of
  395. @ saved stack
  396. mov r13, #MODE_SVC @ prepare SVC-Mode
  397. @ msr spsr_c, r13
  398. msr spsr, r13 @ switch modes, make sure
  399. @ moves will execute
  400. mov lr, pc @ capture return pc
  401. movs pc, lr @ jump to next instruction &
  402. @ switch modes.
  403. .endm
  404. .macro get_bad_stack_swi
  405. sub r13, r13, #4 @ space on current stack for
  406. @ scratch reg.
  407. str r0, [r13] @ save R0's value.
  408. ldr r0, IRQ_STACK_START_IN @ get data regions start
  409. @ spots for abort stack
  410. str lr, [r0] @ save caller lr in position 0
  411. @ of saved stack
  412. mrs r0, spsr @ get the spsr
  413. str lr, [r0, #4] @ save spsr in position 1 of
  414. @ saved stack
  415. ldr r0, [r13] @ restore r0
  416. add r13, r13, #4 @ pop stack entry
  417. .endm
  418. .macro get_irq_stack @ setup IRQ stack
  419. ldr sp, IRQ_STACK_START
  420. .endm
  421. .macro get_fiq_stack @ setup FIQ stack
  422. ldr sp, FIQ_STACK_START
  423. .endm
  424. /*
  425. * exception handlers
  426. */
  427. .align 5
  428. undefined_instruction:
  429. get_bad_stack
  430. bad_save_user_regs
  431. bl do_undefined_instruction
  432. .align 5
  433. software_interrupt:
  434. get_bad_stack_swi
  435. bad_save_user_regs
  436. bl do_software_interrupt
  437. .align 5
  438. prefetch_abort:
  439. get_bad_stack
  440. bad_save_user_regs
  441. bl do_prefetch_abort
  442. .align 5
  443. data_abort:
  444. get_bad_stack
  445. bad_save_user_regs
  446. bl do_data_abort
  447. .align 5
  448. not_used:
  449. get_bad_stack
  450. bad_save_user_regs
  451. bl do_not_used
  452. #ifdef CONFIG_USE_IRQ
  453. .align 5
  454. irq:
  455. get_irq_stack
  456. irq_save_user_regs
  457. bl do_irq
  458. irq_restore_user_regs
  459. .align 5
  460. fiq:
  461. get_fiq_stack
  462. /* someone ought to write a more effective fiq_save_user_regs */
  463. irq_save_user_regs
  464. bl do_fiq
  465. irq_restore_user_regs
  466. #else
  467. .align 5
  468. irq:
  469. get_bad_stack
  470. bad_save_user_regs
  471. bl do_irq
  472. .align 5
  473. fiq:
  474. get_bad_stack
  475. bad_save_user_regs
  476. bl do_fiq
  477. #endif /* CONFIG_USE_IRQ */
  478. #endif /* CONFIG_SPL_BUILD */