sdram.c 11 KB

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  1. /*
  2. * Timing and Organization details of the ddr device parts used in OMAP5
  3. * EVM
  4. *
  5. * (C) Copyright 2010
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Aneesh V <aneesh@ti.com>
  9. * Sricharan R <r.sricharan@ti.com>
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. #include <asm/emif.h>
  30. #include <asm/arch/sys_proto.h>
  31. /*
  32. * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
  33. * EVM. Since the parts used and geometry are identical for
  34. * evm for a given OMAP5 revision, this information is kept
  35. * here instead of being in board directory. However the key functions
  36. * exported are weakly linked so that they can be over-ridden in the board
  37. * directory if there is a OMAP5 board in the future that uses a different
  38. * memory device or geometry.
  39. *
  40. * For any new board with different memory devices over-ride one or more
  41. * of the following functions as per the CONFIG flags you intend to enable:
  42. * - emif_get_reg_dump()
  43. * - emif_get_dmm_regs()
  44. * - emif_get_device_details()
  45. * - emif_get_device_timings()
  46. */
  47. #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  48. const struct emif_regs emif_regs_532_mhz_2cs = {
  49. .sdram_config_init = 0x80800EBA,
  50. .sdram_config = 0x808022BA,
  51. .ref_ctrl = 0x0000081A,
  52. .sdram_tim1 = 0x772F6873,
  53. .sdram_tim2 = 0x304a129a,
  54. .sdram_tim3 = 0x02f7e45f,
  55. .read_idle_ctrl = 0x00050000,
  56. .zq_config = 0x000b3215,
  57. .temp_alert_config = 0x08000a05,
  58. .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
  59. .emif_ddr_phy_ctlr_1 = 0x0E28420d,
  60. .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
  61. .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
  62. .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
  63. .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
  64. .emif_ddr_ext_phy_ctrl_5 = 0x04010040
  65. };
  66. const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
  67. .sdram_config_init = 0x80800EBA,
  68. .sdram_config = 0x808022BA,
  69. .ref_ctrl = 0x0000081A,
  70. .sdram_tim1 = 0x772F6873,
  71. .sdram_tim2 = 0x304a129a,
  72. .sdram_tim3 = 0x02f7e45f,
  73. .read_idle_ctrl = 0x00050000,
  74. .zq_config = 0x100b3215,
  75. .temp_alert_config = 0x08000a05,
  76. .emif_ddr_phy_ctlr_1_init = 0x0E30400d,
  77. .emif_ddr_phy_ctlr_1 = 0x0E30400d,
  78. .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
  79. .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
  80. .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
  81. .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
  82. .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
  83. };
  84. const struct emif_regs emif_regs_266_mhz_2cs = {
  85. .sdram_config_init = 0x80800EBA,
  86. .sdram_config = 0x808022BA,
  87. .ref_ctrl = 0x0000040D,
  88. .sdram_tim1 = 0x2A86B419,
  89. .sdram_tim2 = 0x1025094A,
  90. .sdram_tim3 = 0x026BA22F,
  91. .read_idle_ctrl = 0x00050000,
  92. .zq_config = 0x000b3215,
  93. .temp_alert_config = 0x08000a05,
  94. .emif_ddr_phy_ctlr_1_init = 0x0E28420d,
  95. .emif_ddr_phy_ctlr_1 = 0x0E28420d,
  96. .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
  97. .emif_ddr_ext_phy_ctrl_2 = 0x0A414829,
  98. .emif_ddr_ext_phy_ctrl_3 = 0x14829052,
  99. .emif_ddr_ext_phy_ctrl_4 = 0x000520A4,
  100. .emif_ddr_ext_phy_ctrl_5 = 0x04010040
  101. };
  102. const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
  103. .sdram_config_init = 0x61851B32,
  104. .sdram_config = 0x61851B32,
  105. .ref_ctrl = 0x00001035,
  106. .sdram_tim1 = 0xCCCF36B3,
  107. .sdram_tim2 = 0x308F7FDA,
  108. .sdram_tim3 = 0x027F88A8,
  109. .read_idle_ctrl = 0x00050000,
  110. .zq_config = 0x0007190B,
  111. .temp_alert_config = 0x00000000,
  112. .emif_ddr_phy_ctlr_1_init = 0x0020420A,
  113. .emif_ddr_phy_ctlr_1 = 0x0024420A,
  114. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  115. .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
  116. .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
  117. .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
  118. .emif_ddr_ext_phy_ctrl_5 = 0x04010040,
  119. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  120. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  121. .emif_rd_wr_lvl_ctl = 0x00000000,
  122. .emif_rd_wr_exec_thresh = 0x00000305
  123. };
  124. const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
  125. .sdram_config_init = 0x61851B32,
  126. .sdram_config = 0x61851B32,
  127. .ref_ctrl = 0x00001035,
  128. .sdram_tim1 = 0xCCCF36B3,
  129. .sdram_tim2 = 0x308F7FDA,
  130. .sdram_tim3 = 0x027F88A8,
  131. .read_idle_ctrl = 0x00050000,
  132. .zq_config = 0x1007190B,
  133. .temp_alert_config = 0x00000000,
  134. .emif_ddr_phy_ctlr_1_init = 0x0030400A,
  135. .emif_ddr_phy_ctlr_1 = 0x0034400A,
  136. .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
  137. .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
  138. .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
  139. .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
  140. .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
  141. .emif_rd_wr_lvl_rmp_win = 0x00000000,
  142. .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
  143. .emif_rd_wr_lvl_ctl = 0x00000000,
  144. .emif_rd_wr_exec_thresh = 0x40000305
  145. };
  146. const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
  147. .dmm_lisa_map_0 = 0x0,
  148. .dmm_lisa_map_1 = 0x0,
  149. .dmm_lisa_map_2 = 0x80740300,
  150. .dmm_lisa_map_3 = 0xFF020100,
  151. .is_ma_present = 0x1
  152. };
  153. const struct dmm_lisa_map_regs lisa_map_512M_x_1 = {
  154. .dmm_lisa_map_0 = 0x0,
  155. .dmm_lisa_map_1 = 0x0,
  156. .dmm_lisa_map_2 = 0x0,
  157. .dmm_lisa_map_3 = 0x80500100,
  158. .is_ma_present = 0x1
  159. };
  160. static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
  161. {
  162. switch (omap_revision()) {
  163. case OMAP5430_ES1_0:
  164. *regs = &emif_regs_532_mhz_2cs;
  165. break;
  166. case OMAP5432_ES1_0:
  167. *regs = &emif_regs_ddr3_532_mhz_1cs;
  168. break;
  169. case OMAP5430_ES2_0:
  170. *regs = &emif_regs_532_mhz_2cs_es2;
  171. break;
  172. case OMAP5432_ES2_0:
  173. case DRA752_ES1_0:
  174. default:
  175. *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
  176. }
  177. }
  178. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  179. __attribute__((weak, alias("emif_get_reg_dump_sdp")));
  180. static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
  181. **dmm_lisa_regs)
  182. {
  183. switch (omap_revision()) {
  184. case OMAP5430_ES1_0:
  185. case OMAP5430_ES2_0:
  186. case OMAP5432_ES1_0:
  187. case OMAP5432_ES2_0:
  188. *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
  189. break;
  190. case DRA752_ES1_0:
  191. default:
  192. *dmm_lisa_regs = &lisa_map_512M_x_1;
  193. }
  194. }
  195. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  196. __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
  197. #else
  198. static const struct lpddr2_device_details dev_4G_S4_details = {
  199. .type = LPDDR2_TYPE_S4,
  200. .density = LPDDR2_DENSITY_4Gb,
  201. .io_width = LPDDR2_IO_WIDTH_32,
  202. .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
  203. };
  204. static void emif_get_device_details_sdp(u32 emif_nr,
  205. struct lpddr2_device_details *cs0_device_details,
  206. struct lpddr2_device_details *cs1_device_details)
  207. {
  208. /* EMIF1 & EMIF2 have identical configuration */
  209. *cs0_device_details = dev_4G_S4_details;
  210. *cs1_device_details = dev_4G_S4_details;
  211. }
  212. void emif_get_device_details(u32 emif_nr,
  213. struct lpddr2_device_details *cs0_device_details,
  214. struct lpddr2_device_details *cs1_device_details)
  215. __attribute__((weak, alias("emif_get_device_details_sdp")));
  216. #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
  217. const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
  218. 0x01004010,
  219. 0x00001004,
  220. 0x04010040,
  221. 0x01004010,
  222. 0x00001004,
  223. 0x00000000,
  224. 0x00000000,
  225. 0x00000000,
  226. 0x80080080,
  227. 0x00800800,
  228. 0x08102040,
  229. 0x00000001,
  230. 0x540A8150,
  231. 0xA81502a0,
  232. 0x002A0540,
  233. 0x00000000,
  234. 0x00000000,
  235. 0x00000000,
  236. 0x00000077
  237. };
  238. const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
  239. 0x01004010,
  240. 0x00001004,
  241. 0x04010040,
  242. 0x01004010,
  243. 0x00001004,
  244. 0x00000000,
  245. 0x00000000,
  246. 0x00000000,
  247. 0x80080080,
  248. 0x00800800,
  249. 0x08102040,
  250. 0x00000002,
  251. 0x0,
  252. 0x0,
  253. 0x0,
  254. 0x00000000,
  255. 0x00000000,
  256. 0x00000000,
  257. 0x00000057
  258. };
  259. const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
  260. 0x50D4350D,
  261. 0x00000D43,
  262. 0x04010040,
  263. 0x01004010,
  264. 0x00001004,
  265. 0x00000000,
  266. 0x00000000,
  267. 0x00000000,
  268. 0x80080080,
  269. 0x00800800,
  270. 0x08102040,
  271. 0x00000002,
  272. 0x00000000,
  273. 0x00000000,
  274. 0x00000000,
  275. 0x00000000,
  276. 0x00000000,
  277. 0x00000000,
  278. 0x00000057
  279. };
  280. const struct lpddr2_mr_regs mr_regs = {
  281. .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
  282. .mr2 = 0x6,
  283. .mr3 = 0x1,
  284. .mr10 = MR10_ZQ_ZQINIT,
  285. .mr16 = MR16_REF_FULL_ARRAY
  286. };
  287. static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
  288. {
  289. switch (omap_revision()) {
  290. case OMAP5430_ES1_0:
  291. case OMAP5430_ES2_0:
  292. *regs = ext_phy_ctrl_const_base;
  293. break;
  294. case OMAP5432_ES1_0:
  295. *regs = ddr3_ext_phy_ctrl_const_base_es1;
  296. break;
  297. case OMAP5432_ES2_0:
  298. case DRA752_ES1_0:
  299. default:
  300. *regs = ddr3_ext_phy_ctrl_const_base_es2;
  301. }
  302. }
  303. void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
  304. {
  305. *regs = &mr_regs;
  306. }
  307. void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
  308. {
  309. u32 *ext_phy_ctrl_base = 0;
  310. u32 *emif_ext_phy_ctrl_base = 0;
  311. const u32 *ext_phy_ctrl_const_regs;
  312. u32 i = 0;
  313. struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  314. ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
  315. emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
  316. /* Configure external phy control timing registers */
  317. for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
  318. writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
  319. /* Update shadow registers */
  320. writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
  321. }
  322. /*
  323. * external phy 6-24 registers do not change with
  324. * ddr frequency
  325. */
  326. emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
  327. for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
  328. writel(ext_phy_ctrl_const_regs[i],
  329. emif_ext_phy_ctrl_base++);
  330. /* Update shadow registers */
  331. writel(ext_phy_ctrl_const_regs[i],
  332. emif_ext_phy_ctrl_base++);
  333. }
  334. }
  335. #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
  336. static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
  337. .max_freq = 532000000,
  338. .RL = 8,
  339. .tRPab = 21,
  340. .tRCD = 18,
  341. .tWR = 15,
  342. .tRASmin = 42,
  343. .tRRD = 10,
  344. .tWTRx2 = 15,
  345. .tXSR = 140,
  346. .tXPx2 = 15,
  347. .tRFCab = 130,
  348. .tRTPx2 = 15,
  349. .tCKE = 3,
  350. .tCKESR = 15,
  351. .tZQCS = 90,
  352. .tZQCL = 360,
  353. .tZQINIT = 1000,
  354. .tDQSCKMAXx2 = 11,
  355. .tRASmax = 70,
  356. .tFAW = 50
  357. };
  358. static const struct lpddr2_min_tck min_tck = {
  359. .tRL = 3,
  360. .tRP_AB = 3,
  361. .tRCD = 3,
  362. .tWR = 3,
  363. .tRAS_MIN = 3,
  364. .tRRD = 2,
  365. .tWTR = 2,
  366. .tXP = 2,
  367. .tRTP = 2,
  368. .tCKE = 3,
  369. .tCKESR = 3,
  370. .tFAW = 8
  371. };
  372. static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
  373. &timings_jedec_532_mhz
  374. };
  375. static const struct lpddr2_device_timings dev_4G_S4_timings = {
  376. .ac_timings = ac_timings,
  377. .min_tck = &min_tck,
  378. };
  379. void emif_get_device_timings_sdp(u32 emif_nr,
  380. const struct lpddr2_device_timings **cs0_device_timings,
  381. const struct lpddr2_device_timings **cs1_device_timings)
  382. {
  383. /* Identical devices on EMIF1 & EMIF2 */
  384. *cs0_device_timings = &dev_4G_S4_timings;
  385. *cs1_device_timings = &dev_4G_S4_timings;
  386. }
  387. void emif_get_device_timings(u32 emif_nr,
  388. const struct lpddr2_device_timings **cs0_device_timings,
  389. const struct lpddr2_device_timings **cs1_device_timings)
  390. __attribute__((weak, alias("emif_get_device_timings_sdp")));
  391. #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */