hwinit.c 11 KB

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  1. /*
  2. *
  3. * Functions for omap5 based boards.
  4. *
  5. * (C) Copyright 2011
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Author :
  9. * Aneesh V <aneesh@ti.com>
  10. * Steve Sakoman <steve@sakoman.com>
  11. * Sricharan <r.sricharan@ti.com>
  12. *
  13. * See file CREDITS for list of people who contributed to this
  14. * project.
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation; either version 2 of
  19. * the License, or (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29. * MA 02111-1307 USA
  30. */
  31. #include <common.h>
  32. #include <asm/armv7.h>
  33. #include <asm/arch/cpu.h>
  34. #include <asm/arch/sys_proto.h>
  35. #include <asm/arch/clocks.h>
  36. #include <asm/sizes.h>
  37. #include <asm/utils.h>
  38. #include <asm/arch/gpio.h>
  39. #include <asm/emif.h>
  40. DECLARE_GLOBAL_DATA_PTR;
  41. u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
  42. static struct gpio_bank gpio_bank_54xx[6] = {
  43. { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
  44. { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
  45. { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
  46. { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
  47. { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
  48. { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
  49. };
  50. const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
  51. #ifdef CONFIG_SPL_BUILD
  52. /* LPDDR2 specific IO settings */
  53. static void io_settings_lpddr2(void)
  54. {
  55. const struct ctrl_ioregs *ioregs;
  56. get_ioregs(&ioregs);
  57. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  58. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  59. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  60. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  61. writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  62. writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  63. writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  64. writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  65. writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  66. }
  67. /* DDR3 specific IO settings */
  68. static void io_settings_ddr3(void)
  69. {
  70. u32 io_settings = 0;
  71. const struct ctrl_ioregs *ioregs;
  72. get_ioregs(&ioregs);
  73. writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
  74. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
  75. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
  76. writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
  77. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
  78. writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
  79. writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
  80. writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
  81. writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
  82. /* omap5432 does not use lpddr2 */
  83. writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
  84. writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
  85. writel(ioregs->ctrl_emif_sdram_config_ext,
  86. (*ctrl)->control_emif1_sdram_config_ext);
  87. writel(ioregs->ctrl_emif_sdram_config_ext,
  88. (*ctrl)->control_emif2_sdram_config_ext);
  89. /* Disable DLL select */
  90. io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
  91. & 0xFFEFFFFF);
  92. writel(io_settings,
  93. (*ctrl)->control_port_emif1_sdram_config);
  94. io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
  95. & 0xFFEFFFFF);
  96. writel(io_settings,
  97. (*ctrl)->control_port_emif2_sdram_config);
  98. }
  99. /*
  100. * Some tuning of IOs for optimal power and performance
  101. */
  102. void do_io_settings(void)
  103. {
  104. u32 io_settings = 0, mask = 0;
  105. /* Impedance settings EMMC, C2C 1,2, hsi2 */
  106. mask = (ds_mask << 2) | (ds_mask << 8) |
  107. (ds_mask << 16) | (ds_mask << 18);
  108. io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
  109. (~mask);
  110. io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
  111. (ds_45_ohm << 18) | (ds_60_ohm << 2);
  112. writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
  113. /* Impedance settings Mcspi2 */
  114. mask = (ds_mask << 30);
  115. io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
  116. (~mask);
  117. io_settings |= (ds_60_ohm << 30);
  118. writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
  119. /* Impedance settings C2C 3,4 */
  120. mask = (ds_mask << 14) | (ds_mask << 16);
  121. io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
  122. (~mask);
  123. io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
  124. writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
  125. /* Slew rate settings EMMC, C2C 1,2 */
  126. mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
  127. io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
  128. (~mask);
  129. io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
  130. writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
  131. /* Slew rate settings hsi2, Mcspi2 */
  132. mask = (sc_mask << 24) | (sc_mask << 28);
  133. io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
  134. (~mask);
  135. io_settings |= (sc_fast << 28) | (sc_fast << 24);
  136. writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
  137. /* Slew rate settings C2C 3,4 */
  138. mask = (sc_mask << 16) | (sc_mask << 18);
  139. io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
  140. (~mask);
  141. io_settings |= (sc_na << 16) | (sc_na << 18);
  142. writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
  143. /* impedance and slew rate settings for usb */
  144. mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
  145. (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
  146. io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
  147. (~mask);
  148. io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
  149. (ds_60_ohm << 23) | (sc_fast << 20) |
  150. (sc_fast << 17) | (sc_fast << 14);
  151. writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
  152. if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
  153. io_settings_lpddr2();
  154. else
  155. io_settings_ddr3();
  156. /* Efuse settings */
  157. writel(EFUSE_1, (*ctrl)->control_efuse_1);
  158. writel(EFUSE_2, (*ctrl)->control_efuse_2);
  159. writel(EFUSE_3, (*ctrl)->control_efuse_3);
  160. writel(EFUSE_4, (*ctrl)->control_efuse_4);
  161. }
  162. static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
  163. {0x45, 0x1}, /* 12 MHz */
  164. {-1, -1}, /* 13 MHz */
  165. {0x63, 0x2}, /* 16.8 MHz */
  166. {0x57, 0x2}, /* 19.2 MHz */
  167. {0x20, 0x1}, /* 26 MHz */
  168. {-1, -1}, /* 27 MHz */
  169. {0x41, 0x3} /* 38.4 MHz */
  170. };
  171. void srcomp_enable(void)
  172. {
  173. u32 srcomp_value, mul_factor, div_factor, clk_val, i;
  174. u32 sysclk_ind = get_sys_clk_index();
  175. u32 omap_rev = omap_revision();
  176. mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
  177. div_factor = srcomp_parameters[sysclk_ind].divide_factor;
  178. for (i = 0; i < 4; i++) {
  179. srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
  180. srcomp_value &=
  181. ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
  182. srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
  183. (div_factor << DIVIDE_FACTOR_XS_SHIFT);
  184. writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
  185. }
  186. if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
  187. clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
  188. clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
  189. writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
  190. for (i = 0; i < 4; i++) {
  191. srcomp_value =
  192. readl((*ctrl)->control_srcomp_north_side + i*4);
  193. srcomp_value &= ~PWRDWN_XS_MASK;
  194. writel(srcomp_value,
  195. (*ctrl)->control_srcomp_north_side + i*4);
  196. while (((readl((*ctrl)->control_srcomp_north_side + i*4)
  197. & SRCODE_READ_XS_MASK) >>
  198. SRCODE_READ_XS_SHIFT) == 0)
  199. ;
  200. srcomp_value =
  201. readl((*ctrl)->control_srcomp_north_side + i*4);
  202. srcomp_value &= ~OVERRIDE_XS_MASK;
  203. writel(srcomp_value,
  204. (*ctrl)->control_srcomp_north_side + i*4);
  205. }
  206. } else {
  207. srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
  208. srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
  209. DIVIDE_FACTOR_XS_MASK);
  210. srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
  211. (div_factor << DIVIDE_FACTOR_XS_SHIFT);
  212. writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
  213. for (i = 0; i < 4; i++) {
  214. srcomp_value =
  215. readl((*ctrl)->control_srcomp_north_side + i*4);
  216. srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
  217. writel(srcomp_value,
  218. (*ctrl)->control_srcomp_north_side + i*4);
  219. srcomp_value =
  220. readl((*ctrl)->control_srcomp_north_side + i*4);
  221. srcomp_value &= ~OVERRIDE_XS_MASK;
  222. writel(srcomp_value,
  223. (*ctrl)->control_srcomp_north_side + i*4);
  224. }
  225. srcomp_value =
  226. readl((*ctrl)->control_srcomp_east_side_wkup);
  227. srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
  228. writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
  229. srcomp_value =
  230. readl((*ctrl)->control_srcomp_east_side_wkup);
  231. srcomp_value &= ~OVERRIDE_XS_MASK;
  232. writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
  233. clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
  234. clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
  235. writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
  236. clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
  237. clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
  238. writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
  239. for (i = 0; i < 4; i++) {
  240. while (((readl((*ctrl)->control_srcomp_north_side + i*4)
  241. & SRCODE_READ_XS_MASK) >>
  242. SRCODE_READ_XS_SHIFT) == 0)
  243. ;
  244. srcomp_value =
  245. readl((*ctrl)->control_srcomp_north_side + i*4);
  246. srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
  247. writel(srcomp_value,
  248. (*ctrl)->control_srcomp_north_side + i*4);
  249. }
  250. while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
  251. SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
  252. ;
  253. srcomp_value =
  254. readl((*ctrl)->control_srcomp_east_side_wkup);
  255. srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
  256. writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
  257. }
  258. }
  259. #endif
  260. void config_data_eye_leveling_samples(u32 emif_base)
  261. {
  262. /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
  263. if (emif_base == EMIF1_BASE)
  264. writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
  265. (*ctrl)->control_emif1_sdram_config_ext);
  266. else if (emif_base == EMIF2_BASE)
  267. writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
  268. (*ctrl)->control_emif2_sdram_config_ext);
  269. }
  270. void init_omap_revision(void)
  271. {
  272. /*
  273. * For some of the ES2/ES1 boards ID_CODE is not reliable:
  274. * Also, ES1 and ES2 have different ARM revisions
  275. * So use ARM revision for identification
  276. */
  277. unsigned int rev = cortex_rev();
  278. switch (readl(CONTROL_ID_CODE)) {
  279. case OMAP5430_CONTROL_ID_CODE_ES1_0:
  280. *omap_si_rev = OMAP5430_ES1_0;
  281. if (rev == MIDR_CORTEX_A15_R2P2)
  282. *omap_si_rev = OMAP5430_ES2_0;
  283. break;
  284. case OMAP5432_CONTROL_ID_CODE_ES1_0:
  285. *omap_si_rev = OMAP5432_ES1_0;
  286. if (rev == MIDR_CORTEX_A15_R2P2)
  287. *omap_si_rev = OMAP5432_ES2_0;
  288. break;
  289. case OMAP5430_CONTROL_ID_CODE_ES2_0:
  290. *omap_si_rev = OMAP5430_ES2_0;
  291. break;
  292. case OMAP5432_CONTROL_ID_CODE_ES2_0:
  293. *omap_si_rev = OMAP5432_ES2_0;
  294. break;
  295. case DRA752_CONTROL_ID_CODE_ES1_0:
  296. *omap_si_rev = DRA752_ES1_0;
  297. break;
  298. default:
  299. *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
  300. }
  301. }
  302. void reset_cpu(ulong ignored)
  303. {
  304. u32 omap_rev = omap_revision();
  305. /*
  306. * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
  307. * So use cold reset in case instead.
  308. */
  309. if (omap_rev == OMAP5430_ES1_0)
  310. writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
  311. else
  312. writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
  313. }
  314. u32 warm_reset(void)
  315. {
  316. return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
  317. }