hw_data.c 21 KB

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  1. /*
  2. *
  3. * HW data initialization for OMAP5
  4. *
  5. * (C) Copyright 2013
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Sricharan R <r.sricharan@ti.com>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. #include <common.h>
  29. #include <asm/arch/omap.h>
  30. #include <asm/arch/sys_proto.h>
  31. #include <asm/omap_common.h>
  32. #include <asm/arch/clocks.h>
  33. #include <asm/omap_gpio.h>
  34. #include <asm/io.h>
  35. #include <asm/emif.h>
  36. struct prcm_regs const **prcm =
  37. (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
  38. struct dplls const **dplls_data =
  39. (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
  40. struct vcores_data const **omap_vcores =
  41. (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
  42. struct omap_sys_ctrl_regs const **ctrl =
  43. (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
  44. /* OPP HIGH FREQUENCY for ES2.0 */
  45. static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
  46. {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  47. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  48. {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  49. {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  50. {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  51. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  52. {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  53. };
  54. /* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
  55. static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
  56. {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  57. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  58. {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  59. {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  60. {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  61. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  62. {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  63. };
  64. /* OPP NOM FREQUENCY for ES1.0 */
  65. static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
  66. {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  67. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  68. {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  69. {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  70. {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  71. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  72. {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  73. };
  74. /* OPP LOW FREQUENCY for ES1.0 */
  75. static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
  76. {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  77. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  78. {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  79. {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  80. {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  81. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  82. {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  83. };
  84. /* OPP LOW FREQUENCY for ES2.0 */
  85. static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
  86. {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  87. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  88. {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  89. {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  90. {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  91. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  92. {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  93. };
  94. static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
  95. {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  96. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  97. {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  98. {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  99. {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  100. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  101. {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
  102. {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
  103. };
  104. static const struct dpll_params
  105. core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
  106. {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
  107. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  108. {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
  109. {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
  110. {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
  111. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  112. {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
  113. };
  114. static const struct dpll_params
  115. core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
  116. {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
  117. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  118. {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
  119. {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
  120. {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
  121. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  122. {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
  123. };
  124. static const struct dpll_params
  125. core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
  126. {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */
  127. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  128. {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */
  129. {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */
  130. {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */
  131. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  132. {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */
  133. {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */
  134. };
  135. static const struct dpll_params
  136. core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
  137. {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
  138. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  139. {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
  140. {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
  141. {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
  142. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  143. {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
  144. };
  145. static const struct dpll_params
  146. core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
  147. {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
  148. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  149. {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
  150. {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
  151. {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
  152. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  153. {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
  154. };
  155. static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
  156. {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
  157. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  158. {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
  159. {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
  160. {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
  161. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  162. {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
  163. };
  164. static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
  165. {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
  166. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  167. {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
  168. {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
  169. {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
  170. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  171. {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
  172. };
  173. static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
  174. {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
  175. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  176. {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
  177. {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
  178. {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
  179. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  180. {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
  181. {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */
  182. };
  183. static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
  184. {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  185. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  186. {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  187. {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  188. {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  189. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  190. {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  191. };
  192. /* ABE M & N values with sys_clk as source */
  193. static const struct dpll_params
  194. abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
  195. {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  196. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  197. {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  198. {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  199. {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  200. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  201. {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  202. };
  203. /* ABE M & N values with 32K clock as source */
  204. static const struct dpll_params abe_dpll_params_32k_196608khz = {
  205. 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
  206. };
  207. static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
  208. {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  209. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  210. {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  211. {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  212. {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  213. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  214. {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
  215. {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
  216. };
  217. static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
  218. {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  219. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  220. {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  221. {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  222. {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  223. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  224. {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
  225. {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
  226. };
  227. struct dplls omap5_dplls_es1 = {
  228. .mpu = mpu_dpll_params_800mhz,
  229. .core = core_dpll_params_2128mhz_ddr532,
  230. .per = per_dpll_params_768mhz,
  231. .iva = iva_dpll_params_2330mhz,
  232. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  233. .abe = abe_dpll_params_sysclk_196608khz,
  234. #else
  235. .abe = &abe_dpll_params_32k_196608khz,
  236. #endif
  237. .usb = usb_dpll_params_1920mhz,
  238. .ddr = NULL
  239. };
  240. struct dplls omap5_dplls_es2 = {
  241. .mpu = mpu_dpll_params_1100mhz,
  242. .core = core_dpll_params_2128mhz_ddr532_es2,
  243. .per = per_dpll_params_768mhz_es2,
  244. .iva = iva_dpll_params_2330mhz,
  245. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  246. .abe = abe_dpll_params_sysclk_196608khz,
  247. #else
  248. .abe = &abe_dpll_params_32k_196608khz,
  249. #endif
  250. .usb = usb_dpll_params_1920mhz,
  251. .ddr = NULL
  252. };
  253. struct dplls dra7xx_dplls = {
  254. .mpu = mpu_dpll_params_1ghz,
  255. .core = core_dpll_params_2128mhz_ddr532_dra7xx,
  256. .per = per_dpll_params_768mhz_dra7xx,
  257. .usb = usb_dpll_params_1920mhz,
  258. .ddr = ddr_dpll_params_1066mhz,
  259. };
  260. struct pmic_data palmas = {
  261. .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
  262. .step = 10000, /* 10 mV represented in uV */
  263. /*
  264. * Offset codes 1-6 all give the base voltage in Palmas
  265. * Offset code 0 switches OFF the SMPS
  266. */
  267. .start_code = 6,
  268. };
  269. struct vcores_data omap5430_volts = {
  270. .mpu.value = VDD_MPU,
  271. .mpu.addr = SMPS_REG_ADDR_12_MPU,
  272. .mpu.pmic = &palmas,
  273. .core.value = VDD_CORE,
  274. .core.addr = SMPS_REG_ADDR_8_CORE,
  275. .core.pmic = &palmas,
  276. .mm.value = VDD_MM,
  277. .mm.addr = SMPS_REG_ADDR_45_IVA,
  278. .mm.pmic = &palmas,
  279. };
  280. struct vcores_data omap5430_volts_es2 = {
  281. .mpu.value = VDD_MPU_ES2,
  282. .mpu.addr = SMPS_REG_ADDR_12_MPU,
  283. .mpu.pmic = &palmas,
  284. .core.value = VDD_CORE_ES2,
  285. .core.addr = SMPS_REG_ADDR_8_CORE,
  286. .core.pmic = &palmas,
  287. .mm.value = VDD_MM_ES2,
  288. .mm.addr = SMPS_REG_ADDR_45_IVA,
  289. .mm.pmic = &palmas,
  290. };
  291. /*
  292. * Enable essential clock domains, modules and
  293. * do some additional special settings needed
  294. */
  295. void enable_basic_clocks(void)
  296. {
  297. u32 const clk_domains_essential[] = {
  298. (*prcm)->cm_l4per_clkstctrl,
  299. (*prcm)->cm_l3init_clkstctrl,
  300. (*prcm)->cm_memif_clkstctrl,
  301. (*prcm)->cm_l4cfg_clkstctrl,
  302. 0
  303. };
  304. u32 const clk_modules_hw_auto_essential[] = {
  305. (*prcm)->cm_l3_gpmc_clkctrl,
  306. (*prcm)->cm_memif_emif_1_clkctrl,
  307. (*prcm)->cm_memif_emif_2_clkctrl,
  308. (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
  309. (*prcm)->cm_wkup_gpio1_clkctrl,
  310. (*prcm)->cm_l4per_gpio2_clkctrl,
  311. (*prcm)->cm_l4per_gpio3_clkctrl,
  312. (*prcm)->cm_l4per_gpio4_clkctrl,
  313. (*prcm)->cm_l4per_gpio5_clkctrl,
  314. (*prcm)->cm_l4per_gpio6_clkctrl,
  315. 0
  316. };
  317. u32 const clk_modules_explicit_en_essential[] = {
  318. (*prcm)->cm_wkup_gptimer1_clkctrl,
  319. (*prcm)->cm_l3init_hsmmc1_clkctrl,
  320. (*prcm)->cm_l3init_hsmmc2_clkctrl,
  321. (*prcm)->cm_l4per_gptimer2_clkctrl,
  322. (*prcm)->cm_wkup_wdtimer2_clkctrl,
  323. (*prcm)->cm_l4per_uart3_clkctrl,
  324. (*prcm)->cm_l4per_i2c1_clkctrl,
  325. 0
  326. };
  327. /* Enable optional additional functional clock for GPIO4 */
  328. setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
  329. GPIO4_CLKCTRL_OPTFCLKEN_MASK);
  330. /* Enable 96 MHz clock for MMC1 & MMC2 */
  331. setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
  332. HSMMC_CLKCTRL_CLKSEL_MASK);
  333. setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
  334. HSMMC_CLKCTRL_CLKSEL_MASK);
  335. /* Set the correct clock dividers for mmc */
  336. setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
  337. HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
  338. setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
  339. HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
  340. /* Select 32KHz clock as the source of GPTIMER1 */
  341. setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
  342. GPTIMER1_CLKCTRL_CLKSEL_MASK);
  343. do_enable_clocks(clk_domains_essential,
  344. clk_modules_hw_auto_essential,
  345. clk_modules_explicit_en_essential,
  346. 1);
  347. /* Select 384Mhz for GPU as its the POR for ES1.0 */
  348. setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
  349. CLKSEL_GPU_HYD_GCLK_MASK);
  350. setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
  351. CLKSEL_GPU_CORE_GCLK_MASK);
  352. /* Enable SCRM OPT clocks for PER and CORE dpll */
  353. setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
  354. OPTFCLKEN_SCRM_PER_MASK);
  355. setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
  356. OPTFCLKEN_SCRM_CORE_MASK);
  357. }
  358. void enable_basic_uboot_clocks(void)
  359. {
  360. u32 const clk_domains_essential[] = {
  361. 0
  362. };
  363. u32 const clk_modules_hw_auto_essential[] = {
  364. 0
  365. };
  366. u32 const clk_modules_explicit_en_essential[] = {
  367. (*prcm)->cm_l4per_mcspi1_clkctrl,
  368. (*prcm)->cm_l4per_i2c2_clkctrl,
  369. (*prcm)->cm_l4per_i2c3_clkctrl,
  370. (*prcm)->cm_l4per_i2c4_clkctrl,
  371. (*prcm)->cm_l3init_hsusbtll_clkctrl,
  372. (*prcm)->cm_l3init_hsusbhost_clkctrl,
  373. (*prcm)->cm_l3init_fsusb_clkctrl,
  374. 0
  375. };
  376. do_enable_clocks(clk_domains_essential,
  377. clk_modules_hw_auto_essential,
  378. clk_modules_explicit_en_essential,
  379. 1);
  380. }
  381. /*
  382. * Enable non-essential clock domains, modules and
  383. * do some additional special settings needed
  384. */
  385. void enable_non_essential_clocks(void)
  386. {
  387. u32 const clk_domains_non_essential[] = {
  388. (*prcm)->cm_mpu_m3_clkstctrl,
  389. (*prcm)->cm_ivahd_clkstctrl,
  390. (*prcm)->cm_dsp_clkstctrl,
  391. (*prcm)->cm_dss_clkstctrl,
  392. (*prcm)->cm_sgx_clkstctrl,
  393. (*prcm)->cm1_abe_clkstctrl,
  394. (*prcm)->cm_c2c_clkstctrl,
  395. (*prcm)->cm_cam_clkstctrl,
  396. (*prcm)->cm_dss_clkstctrl,
  397. (*prcm)->cm_sdma_clkstctrl,
  398. 0
  399. };
  400. u32 const clk_modules_hw_auto_non_essential[] = {
  401. (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
  402. (*prcm)->cm_ivahd_ivahd_clkctrl,
  403. (*prcm)->cm_ivahd_sl2_clkctrl,
  404. (*prcm)->cm_dsp_dsp_clkctrl,
  405. (*prcm)->cm_l3instr_l3_3_clkctrl,
  406. (*prcm)->cm_l3instr_l3_instr_clkctrl,
  407. (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
  408. (*prcm)->cm_l3init_hsi_clkctrl,
  409. (*prcm)->cm_l4per_hdq1w_clkctrl,
  410. 0
  411. };
  412. u32 const clk_modules_explicit_en_non_essential[] = {
  413. (*prcm)->cm1_abe_aess_clkctrl,
  414. (*prcm)->cm1_abe_pdm_clkctrl,
  415. (*prcm)->cm1_abe_dmic_clkctrl,
  416. (*prcm)->cm1_abe_mcasp_clkctrl,
  417. (*prcm)->cm1_abe_mcbsp1_clkctrl,
  418. (*prcm)->cm1_abe_mcbsp2_clkctrl,
  419. (*prcm)->cm1_abe_mcbsp3_clkctrl,
  420. (*prcm)->cm1_abe_slimbus_clkctrl,
  421. (*prcm)->cm1_abe_timer5_clkctrl,
  422. (*prcm)->cm1_abe_timer6_clkctrl,
  423. (*prcm)->cm1_abe_timer7_clkctrl,
  424. (*prcm)->cm1_abe_timer8_clkctrl,
  425. (*prcm)->cm1_abe_wdt3_clkctrl,
  426. (*prcm)->cm_l4per_gptimer9_clkctrl,
  427. (*prcm)->cm_l4per_gptimer10_clkctrl,
  428. (*prcm)->cm_l4per_gptimer11_clkctrl,
  429. (*prcm)->cm_l4per_gptimer3_clkctrl,
  430. (*prcm)->cm_l4per_gptimer4_clkctrl,
  431. (*prcm)->cm_l4per_mcspi2_clkctrl,
  432. (*prcm)->cm_l4per_mcspi3_clkctrl,
  433. (*prcm)->cm_l4per_mcspi4_clkctrl,
  434. (*prcm)->cm_l4per_mmcsd3_clkctrl,
  435. (*prcm)->cm_l4per_mmcsd4_clkctrl,
  436. (*prcm)->cm_l4per_mmcsd5_clkctrl,
  437. (*prcm)->cm_l4per_uart1_clkctrl,
  438. (*prcm)->cm_l4per_uart2_clkctrl,
  439. (*prcm)->cm_l4per_uart4_clkctrl,
  440. (*prcm)->cm_wkup_keyboard_clkctrl,
  441. (*prcm)->cm_wkup_wdtimer2_clkctrl,
  442. (*prcm)->cm_cam_iss_clkctrl,
  443. (*prcm)->cm_cam_fdif_clkctrl,
  444. (*prcm)->cm_dss_dss_clkctrl,
  445. (*prcm)->cm_sgx_sgx_clkctrl,
  446. 0
  447. };
  448. /* Enable optional functional clock for ISS */
  449. setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
  450. /* Enable all optional functional clocks of DSS */
  451. setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
  452. do_enable_clocks(clk_domains_non_essential,
  453. clk_modules_hw_auto_non_essential,
  454. clk_modules_explicit_en_non_essential,
  455. 0);
  456. /* Put camera module in no sleep mode */
  457. clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
  458. MODULE_CLKCTRL_MODULEMODE_MASK,
  459. CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
  460. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  461. }
  462. const struct ctrl_ioregs ioregs_omap5430 = {
  463. .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
  464. .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
  465. .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
  466. .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
  467. .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
  468. };
  469. const struct ctrl_ioregs ioregs_omap5432_es1 = {
  470. .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
  471. .ctrl_lpddr2ch = 0x0,
  472. .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
  473. .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
  474. .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
  475. .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
  476. .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
  477. };
  478. const struct ctrl_ioregs ioregs_omap5432_es2 = {
  479. .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
  480. .ctrl_lpddr2ch = 0x0,
  481. .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
  482. .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
  483. .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
  484. .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
  485. .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
  486. };
  487. void hw_data_init(void)
  488. {
  489. u32 omap_rev = omap_revision();
  490. switch (omap_rev) {
  491. case OMAP5430_ES1_0:
  492. case OMAP5432_ES1_0:
  493. *prcm = &omap5_es1_prcm;
  494. *dplls_data = &omap5_dplls_es1;
  495. *omap_vcores = &omap5430_volts;
  496. *ctrl = &omap5_ctrl;
  497. break;
  498. case OMAP5430_ES2_0:
  499. case OMAP5432_ES2_0:
  500. *prcm = &omap5_es2_prcm;
  501. *dplls_data = &omap5_dplls_es2;
  502. *omap_vcores = &omap5430_volts_es2;
  503. *ctrl = &omap5_ctrl;
  504. break;
  505. case DRA752_ES1_0:
  506. *prcm = &dra7xx_prcm;
  507. *dplls_data = &dra7xx_dplls;
  508. *omap_vcores = &omap5430_volts_es2;
  509. *ctrl = &dra7xx_ctrl;
  510. break;
  511. default:
  512. printf("\n INVALID OMAP REVISION ");
  513. }
  514. }
  515. void get_ioregs(const struct ctrl_ioregs **regs)
  516. {
  517. u32 omap_rev = omap_revision();
  518. switch (omap_rev) {
  519. case OMAP5430_ES1_0:
  520. case OMAP5430_ES2_0:
  521. *regs = &ioregs_omap5430;
  522. break;
  523. case OMAP5432_ES1_0:
  524. *regs = &ioregs_omap5432_es1;
  525. break;
  526. case OMAP5432_ES2_0:
  527. case DRA752_ES1_0:
  528. *regs = &ioregs_omap5432_es2;
  529. break;
  530. default:
  531. printf("\n INVALID OMAP REVISION ");
  532. }
  533. }