sdram_elpida.c 7.9 KB

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  1. /*
  2. * Timing and Organization details of the Elpida parts used in OMAP4
  3. * SDPs and Panda
  4. *
  5. * (C) Copyright 2010
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Aneesh V <aneesh@ti.com>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. #include <asm/emif.h>
  29. #include <asm/arch/sys_proto.h>
  30. /*
  31. * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
  32. * SDP and Panda. Since the parts used and geometry are identical for
  33. * SDP and Panda for a given OMAP4 revision, this information is kept
  34. * here instead of being in board directory. However the key functions
  35. * exported are weakly linked so that they can be over-ridden in the board
  36. * directory if there is a OMAP4 board in the future that uses a different
  37. * memory device or geometry.
  38. *
  39. * For any new board with different memory devices over-ride one or more
  40. * of the following functions as per the CONFIG flags you intend to enable:
  41. * - emif_get_reg_dump()
  42. * - emif_get_dmm_regs()
  43. * - emif_get_device_details()
  44. * - emif_get_device_timings()
  45. */
  46. #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  47. static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
  48. .sdram_config_init = 0x80000eb9,
  49. .sdram_config = 0x80001ab9,
  50. .ref_ctrl = 0x0000030c,
  51. .sdram_tim1 = 0x08648311,
  52. .sdram_tim2 = 0x101b06ca,
  53. .sdram_tim3 = 0x0048a19f,
  54. .read_idle_ctrl = 0x000501ff,
  55. .zq_config = 0x500b3214,
  56. .temp_alert_config = 0xd8016893,
  57. .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
  58. .emif_ddr_phy_ctlr_1 = 0x049ff808
  59. };
  60. static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
  61. .sdram_config_init = 0x80000eb1,
  62. .sdram_config = 0x80001ab1,
  63. .ref_ctrl = 0x000005cd,
  64. .sdram_tim1 = 0x10cb0622,
  65. .sdram_tim2 = 0x20350d52,
  66. .sdram_tim3 = 0x00b1431f,
  67. .read_idle_ctrl = 0x000501ff,
  68. .zq_config = 0x500b3214,
  69. .temp_alert_config = 0x58016893,
  70. .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
  71. .emif_ddr_phy_ctlr_1 = 0x049ff418
  72. };
  73. const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
  74. .sdram_config_init = 0x80000eb9,
  75. .sdram_config = 0x80001ab9,
  76. .ref_ctrl = 0x00000618,
  77. .sdram_tim1 = 0x10eb0662,
  78. .sdram_tim2 = 0x20370dd2,
  79. .sdram_tim3 = 0x00b1c33f,
  80. .read_idle_ctrl = 0x000501ff,
  81. .zq_config = 0xd00b3214,
  82. .temp_alert_config = 0xd8016893,
  83. .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
  84. .emif_ddr_phy_ctlr_1 = 0x049ff418
  85. };
  86. const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
  87. .dmm_lisa_map_0 = 0xFF020100,
  88. .dmm_lisa_map_1 = 0,
  89. .dmm_lisa_map_2 = 0,
  90. .dmm_lisa_map_3 = 0x80540300,
  91. .is_ma_present = 0x0
  92. };
  93. const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
  94. .dmm_lisa_map_0 = 0xFF020100,
  95. .dmm_lisa_map_1 = 0,
  96. .dmm_lisa_map_2 = 0,
  97. .dmm_lisa_map_3 = 0x80640300,
  98. .is_ma_present = 0x0
  99. };
  100. const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
  101. .dmm_lisa_map_0 = 0xFF020100,
  102. .dmm_lisa_map_1 = 0,
  103. .dmm_lisa_map_2 = 0,
  104. .dmm_lisa_map_3 = 0x80640300,
  105. .is_ma_present = 0x1
  106. };
  107. static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
  108. {
  109. u32 omap4_rev = omap_revision();
  110. /* Same devices and geometry on both EMIFs */
  111. if (omap4_rev == OMAP4430_ES1_0)
  112. *regs = &emif_regs_elpida_380_mhz_1cs;
  113. else if (omap4_rev == OMAP4430_ES2_0)
  114. *regs = &emif_regs_elpida_200_mhz_2cs;
  115. else
  116. *regs = &emif_regs_elpida_400_mhz_2cs;
  117. }
  118. void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
  119. __attribute__((weak, alias("emif_get_reg_dump_sdp")));
  120. static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
  121. **dmm_lisa_regs)
  122. {
  123. u32 omap_rev = omap_revision();
  124. if (omap_rev == OMAP4430_ES1_0)
  125. *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
  126. else if (omap_rev < OMAP4460_ES1_0)
  127. *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
  128. else
  129. *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
  130. }
  131. void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
  132. __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
  133. #else
  134. static const struct lpddr2_device_details elpida_2G_S4_details = {
  135. .type = LPDDR2_TYPE_S4,
  136. .density = LPDDR2_DENSITY_2Gb,
  137. .io_width = LPDDR2_IO_WIDTH_32,
  138. .manufacturer = LPDDR2_MANUFACTURER_ELPIDA
  139. };
  140. struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
  141. struct lpddr2_device_details *lpddr2_dev_details)
  142. {
  143. u32 omap_rev = omap_revision();
  144. /* EMIF1 & EMIF2 have identical configuration */
  145. if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
  146. /* Nothing connected on CS1 for ES1.0 */
  147. return NULL;
  148. } else {
  149. /* In all other cases Elpida 2G device */
  150. *lpddr2_dev_details = elpida_2G_S4_details;
  151. return lpddr2_dev_details;
  152. }
  153. }
  154. struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
  155. struct lpddr2_device_details *lpddr2_dev_details)
  156. __attribute__((weak, alias("emif_get_device_details_sdp")));
  157. #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
  158. #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
  159. static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
  160. .max_freq = 400000000,
  161. .RL = 6,
  162. .tRPab = 21,
  163. .tRCD = 18,
  164. .tWR = 15,
  165. .tRASmin = 42,
  166. .tRRD = 10,
  167. .tWTRx2 = 15,
  168. .tXSR = 140,
  169. .tXPx2 = 15,
  170. .tRFCab = 130,
  171. .tRTPx2 = 15,
  172. .tCKE = 3,
  173. .tCKESR = 15,
  174. .tZQCS = 90,
  175. .tZQCL = 360,
  176. .tZQINIT = 1000,
  177. .tDQSCKMAXx2 = 11,
  178. .tRASmax = 70,
  179. .tFAW = 50
  180. };
  181. static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
  182. .max_freq = 333000000,
  183. .RL = 5,
  184. .tRPab = 21,
  185. .tRCD = 18,
  186. .tWR = 15,
  187. .tRASmin = 42,
  188. .tRRD = 10,
  189. .tWTRx2 = 15,
  190. .tXSR = 140,
  191. .tXPx2 = 15,
  192. .tRFCab = 130,
  193. .tRTPx2 = 15,
  194. .tCKE = 3,
  195. .tCKESR = 15,
  196. .tZQCS = 90,
  197. .tZQCL = 360,
  198. .tZQINIT = 1000,
  199. .tDQSCKMAXx2 = 11,
  200. .tRASmax = 70,
  201. .tFAW = 50
  202. };
  203. static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
  204. .max_freq = 200000000,
  205. .RL = 3,
  206. .tRPab = 21,
  207. .tRCD = 18,
  208. .tWR = 15,
  209. .tRASmin = 42,
  210. .tRRD = 10,
  211. .tWTRx2 = 20,
  212. .tXSR = 140,
  213. .tXPx2 = 15,
  214. .tRFCab = 130,
  215. .tRTPx2 = 15,
  216. .tCKE = 3,
  217. .tCKESR = 15,
  218. .tZQCS = 90,
  219. .tZQCL = 360,
  220. .tZQINIT = 1000,
  221. .tDQSCKMAXx2 = 11,
  222. .tRASmax = 70,
  223. .tFAW = 50
  224. };
  225. static const struct lpddr2_min_tck min_tck_elpida = {
  226. .tRL = 3,
  227. .tRP_AB = 3,
  228. .tRCD = 3,
  229. .tWR = 3,
  230. .tRAS_MIN = 3,
  231. .tRRD = 2,
  232. .tWTR = 2,
  233. .tXP = 2,
  234. .tRTP = 2,
  235. .tCKE = 3,
  236. .tCKESR = 3,
  237. .tFAW = 8
  238. };
  239. static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
  240. &timings_elpida_200_mhz,
  241. &timings_elpida_333_mhz,
  242. &timings_elpida_400_mhz
  243. };
  244. static const struct lpddr2_device_timings elpida_2G_S4_timings = {
  245. .ac_timings = elpida_ac_timings,
  246. .min_tck = &min_tck_elpida,
  247. };
  248. void emif_get_device_timings_sdp(u32 emif_nr,
  249. const struct lpddr2_device_timings **cs0_device_timings,
  250. const struct lpddr2_device_timings **cs1_device_timings)
  251. {
  252. u32 omap_rev = omap_revision();
  253. /* Identical devices on EMIF1 & EMIF2 */
  254. *cs0_device_timings = &elpida_2G_S4_timings;
  255. if (omap_rev == OMAP4430_ES1_0)
  256. *cs1_device_timings = NULL;
  257. else
  258. *cs1_device_timings = &elpida_2G_S4_timings;
  259. }
  260. void emif_get_device_timings(u32 emif_nr,
  261. const struct lpddr2_device_timings **cs0_device_timings,
  262. const struct lpddr2_device_timings **cs1_device_timings)
  263. __attribute__((weak, alias("emif_get_device_timings_sdp")));
  264. #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
  265. const struct lpddr2_mr_regs mr_regs = {
  266. .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
  267. .mr2 = 0x4,
  268. .mr3 = -1,
  269. .mr10 = MR10_ZQ_ZQINIT,
  270. .mr16 = MR16_REF_FULL_ARRAY
  271. };
  272. void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
  273. {
  274. *regs = &mr_regs;
  275. }