hw_data.c 15 KB

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  1. /*
  2. *
  3. * HW data initialization for OMAP4
  4. *
  5. * (C) Copyright 2013
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Sricharan R <r.sricharan@ti.com>
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. #include <common.h>
  29. #include <asm/arch/omap.h>
  30. #include <asm/arch/sys_proto.h>
  31. #include <asm/omap_common.h>
  32. #include <asm/arch/clocks.h>
  33. #include <asm/omap_gpio.h>
  34. #include <asm/io.h>
  35. struct prcm_regs const **prcm =
  36. (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
  37. struct dplls const **dplls_data =
  38. (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
  39. struct vcores_data const **omap_vcores =
  40. (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
  41. struct omap_sys_ctrl_regs const **ctrl =
  42. (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
  43. /*
  44. * The M & N values in the following tables are created using the
  45. * following tool:
  46. * tools/omap/clocks_get_m_n.c
  47. * Please use this tool for creating the table for any new frequency.
  48. */
  49. /*
  50. * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
  51. * OMAP4460 OPP_NOM frequency
  52. */
  53. static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
  54. {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  55. {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  56. {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  57. {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  58. {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  59. {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  60. {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  61. };
  62. /*
  63. * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
  64. * OMAP4430 OPP_TURBO frequency
  65. */
  66. static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
  67. {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  68. {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  69. {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  70. {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  71. {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  72. {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  73. {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  74. };
  75. /*
  76. * dpll locked at 1200 MHz - MPU clk at 600 MHz
  77. * OMAP4430 OPP_NOM frequency
  78. */
  79. static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
  80. {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  81. {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  82. {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  83. {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  84. {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  85. {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  86. {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  87. };
  88. /* OMAP4460 OPP_NOM frequency */
  89. static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
  90. {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
  91. {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
  92. {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
  93. {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  94. {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
  95. {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
  96. {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
  97. };
  98. /* OMAP4430 ES1 OPP_NOM frequency */
  99. static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
  100. {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
  101. {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
  102. {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
  103. {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  104. {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
  105. {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
  106. {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
  107. };
  108. /* OMAP4430 ES2.X OPP_NOM frequency */
  109. static const struct dpll_params
  110. core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
  111. {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
  112. {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
  113. {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
  114. {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  115. {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
  116. {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
  117. {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
  118. };
  119. static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
  120. {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
  121. {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
  122. {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
  123. {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
  124. {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
  125. {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
  126. {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
  127. };
  128. static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
  129. {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  130. {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  131. {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  132. {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  133. {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  134. {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  135. {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  136. };
  137. /* ABE M & N values with sys_clk as source */
  138. static const struct dpll_params
  139. abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
  140. {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  141. {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  142. {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  143. {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  144. {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  145. {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  146. {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  147. };
  148. /* ABE M & N values with 32K clock as source */
  149. static const struct dpll_params abe_dpll_params_32k_196608khz = {
  150. 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
  151. };
  152. static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
  153. {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  154. {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  155. {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  156. {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  157. {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  158. {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  159. {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  160. };
  161. struct dplls omap4430_dplls_es1 = {
  162. .mpu = mpu_dpll_params_1200mhz,
  163. .core = core_dpll_params_es1_1524mhz,
  164. .per = per_dpll_params_1536mhz,
  165. .iva = iva_dpll_params_1862mhz,
  166. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  167. .abe = abe_dpll_params_sysclk_196608khz,
  168. #else
  169. .abe = &abe_dpll_params_32k_196608khz,
  170. #endif
  171. .usb = usb_dpll_params_1920mhz,
  172. .ddr = NULL
  173. };
  174. struct dplls omap4430_dplls = {
  175. .mpu = mpu_dpll_params_1200mhz,
  176. .core = core_dpll_params_1600mhz,
  177. .per = per_dpll_params_1536mhz,
  178. .iva = iva_dpll_params_1862mhz,
  179. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  180. .abe = abe_dpll_params_sysclk_196608khz,
  181. #else
  182. .abe = &abe_dpll_params_32k_196608khz,
  183. #endif
  184. .usb = usb_dpll_params_1920mhz,
  185. .ddr = NULL
  186. };
  187. struct dplls omap4460_dplls = {
  188. .mpu = mpu_dpll_params_1400mhz,
  189. .core = core_dpll_params_1600mhz,
  190. .per = per_dpll_params_1536mhz,
  191. .iva = iva_dpll_params_1862mhz,
  192. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  193. .abe = abe_dpll_params_sysclk_196608khz,
  194. #else
  195. .abe = &abe_dpll_params_32k_196608khz,
  196. #endif
  197. .usb = usb_dpll_params_1920mhz,
  198. .ddr = NULL
  199. };
  200. struct pmic_data twl6030_4430es1 = {
  201. .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
  202. .step = 12660, /* 10 mV represented in uV */
  203. /* The code starts at 1 not 0 */
  204. .start_code = 1,
  205. };
  206. struct pmic_data twl6030 = {
  207. .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
  208. .step = 12660, /* 10 mV represented in uV */
  209. /* The code starts at 1 not 0 */
  210. .start_code = 1,
  211. };
  212. struct pmic_data tps62361 = {
  213. .base_offset = TPS62361_BASE_VOLT_MV,
  214. .step = 10000, /* 10 mV represented in uV */
  215. .start_code = 0,
  216. .gpio = TPS62361_VSEL0_GPIO,
  217. .gpio_en = 1
  218. };
  219. struct vcores_data omap4430_volts_es1 = {
  220. .mpu.value = 1325,
  221. .mpu.addr = SMPS_REG_ADDR_VCORE1,
  222. .mpu.pmic = &twl6030_4430es1,
  223. .core.value = 1200,
  224. .core.addr = SMPS_REG_ADDR_VCORE3,
  225. .core.pmic = &twl6030_4430es1,
  226. .mm.value = 1200,
  227. .mm.addr = SMPS_REG_ADDR_VCORE2,
  228. .mm.pmic = &twl6030_4430es1,
  229. };
  230. struct vcores_data omap4430_volts = {
  231. .mpu.value = 1325,
  232. .mpu.addr = SMPS_REG_ADDR_VCORE1,
  233. .mpu.pmic = &twl6030,
  234. .core.value = 1200,
  235. .core.addr = SMPS_REG_ADDR_VCORE3,
  236. .core.pmic = &twl6030,
  237. .mm.value = 1200,
  238. .mm.addr = SMPS_REG_ADDR_VCORE2,
  239. .mm.pmic = &twl6030,
  240. };
  241. struct vcores_data omap4460_volts = {
  242. .mpu.value = 1203,
  243. .mpu.addr = TPS62361_REG_ADDR_SET1,
  244. .mpu.pmic = &tps62361,
  245. .core.value = 1200,
  246. .core.addr = SMPS_REG_ADDR_VCORE1,
  247. .core.pmic = &tps62361,
  248. .mm.value = 1200,
  249. .mm.addr = SMPS_REG_ADDR_VCORE2,
  250. .mm.pmic = &tps62361,
  251. };
  252. /*
  253. * Enable essential clock domains, modules and
  254. * do some additional special settings needed
  255. */
  256. void enable_basic_clocks(void)
  257. {
  258. u32 const clk_domains_essential[] = {
  259. (*prcm)->cm_l4per_clkstctrl,
  260. (*prcm)->cm_l3init_clkstctrl,
  261. (*prcm)->cm_memif_clkstctrl,
  262. (*prcm)->cm_l4cfg_clkstctrl,
  263. 0
  264. };
  265. u32 const clk_modules_hw_auto_essential[] = {
  266. (*prcm)->cm_l3_gpmc_clkctrl,
  267. (*prcm)->cm_memif_emif_1_clkctrl,
  268. (*prcm)->cm_memif_emif_2_clkctrl,
  269. (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
  270. (*prcm)->cm_wkup_gpio1_clkctrl,
  271. (*prcm)->cm_l4per_gpio2_clkctrl,
  272. (*prcm)->cm_l4per_gpio3_clkctrl,
  273. (*prcm)->cm_l4per_gpio4_clkctrl,
  274. (*prcm)->cm_l4per_gpio5_clkctrl,
  275. (*prcm)->cm_l4per_gpio6_clkctrl,
  276. 0
  277. };
  278. u32 const clk_modules_explicit_en_essential[] = {
  279. (*prcm)->cm_wkup_gptimer1_clkctrl,
  280. (*prcm)->cm_l3init_hsmmc1_clkctrl,
  281. (*prcm)->cm_l3init_hsmmc2_clkctrl,
  282. (*prcm)->cm_l4per_gptimer2_clkctrl,
  283. (*prcm)->cm_wkup_wdtimer2_clkctrl,
  284. (*prcm)->cm_l4per_uart3_clkctrl,
  285. 0
  286. };
  287. /* Enable optional additional functional clock for GPIO4 */
  288. setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
  289. GPIO4_CLKCTRL_OPTFCLKEN_MASK);
  290. /* Enable 96 MHz clock for MMC1 & MMC2 */
  291. setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
  292. HSMMC_CLKCTRL_CLKSEL_MASK);
  293. setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
  294. HSMMC_CLKCTRL_CLKSEL_MASK);
  295. /* Select 32KHz clock as the source of GPTIMER1 */
  296. setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
  297. GPTIMER1_CLKCTRL_CLKSEL_MASK);
  298. /* Enable optional 48M functional clock for USB PHY */
  299. setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
  300. USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
  301. do_enable_clocks(clk_domains_essential,
  302. clk_modules_hw_auto_essential,
  303. clk_modules_explicit_en_essential,
  304. 1);
  305. }
  306. void enable_basic_uboot_clocks(void)
  307. {
  308. u32 const clk_domains_essential[] = {
  309. 0
  310. };
  311. u32 const clk_modules_hw_auto_essential[] = {
  312. (*prcm)->cm_l3init_hsusbotg_clkctrl,
  313. (*prcm)->cm_l3init_usbphy_clkctrl,
  314. (*prcm)->cm_l3init_usbphy_clkctrl,
  315. (*prcm)->cm_clksel_usb_60mhz,
  316. (*prcm)->cm_l3init_hsusbtll_clkctrl,
  317. 0
  318. };
  319. u32 const clk_modules_explicit_en_essential[] = {
  320. (*prcm)->cm_l4per_mcspi1_clkctrl,
  321. (*prcm)->cm_l4per_i2c1_clkctrl,
  322. (*prcm)->cm_l4per_i2c2_clkctrl,
  323. (*prcm)->cm_l4per_i2c3_clkctrl,
  324. (*prcm)->cm_l4per_i2c4_clkctrl,
  325. (*prcm)->cm_l3init_hsusbhost_clkctrl,
  326. 0
  327. };
  328. do_enable_clocks(clk_domains_essential,
  329. clk_modules_hw_auto_essential,
  330. clk_modules_explicit_en_essential,
  331. 1);
  332. }
  333. /*
  334. * Enable non-essential clock domains, modules and
  335. * do some additional special settings needed
  336. */
  337. void enable_non_essential_clocks(void)
  338. {
  339. u32 const clk_domains_non_essential[] = {
  340. (*prcm)->cm_mpu_m3_clkstctrl,
  341. (*prcm)->cm_ivahd_clkstctrl,
  342. (*prcm)->cm_dsp_clkstctrl,
  343. (*prcm)->cm_dss_clkstctrl,
  344. (*prcm)->cm_sgx_clkstctrl,
  345. (*prcm)->cm1_abe_clkstctrl,
  346. (*prcm)->cm_c2c_clkstctrl,
  347. (*prcm)->cm_cam_clkstctrl,
  348. (*prcm)->cm_dss_clkstctrl,
  349. (*prcm)->cm_sdma_clkstctrl,
  350. 0
  351. };
  352. u32 const clk_modules_hw_auto_non_essential[] = {
  353. (*prcm)->cm_l3instr_l3_3_clkctrl,
  354. (*prcm)->cm_l3instr_l3_instr_clkctrl,
  355. (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
  356. (*prcm)->cm_l3init_hsi_clkctrl,
  357. 0
  358. };
  359. u32 const clk_modules_explicit_en_non_essential[] = {
  360. (*prcm)->cm1_abe_aess_clkctrl,
  361. (*prcm)->cm1_abe_pdm_clkctrl,
  362. (*prcm)->cm1_abe_dmic_clkctrl,
  363. (*prcm)->cm1_abe_mcasp_clkctrl,
  364. (*prcm)->cm1_abe_mcbsp1_clkctrl,
  365. (*prcm)->cm1_abe_mcbsp2_clkctrl,
  366. (*prcm)->cm1_abe_mcbsp3_clkctrl,
  367. (*prcm)->cm1_abe_slimbus_clkctrl,
  368. (*prcm)->cm1_abe_timer5_clkctrl,
  369. (*prcm)->cm1_abe_timer6_clkctrl,
  370. (*prcm)->cm1_abe_timer7_clkctrl,
  371. (*prcm)->cm1_abe_timer8_clkctrl,
  372. (*prcm)->cm1_abe_wdt3_clkctrl,
  373. (*prcm)->cm_l4per_gptimer9_clkctrl,
  374. (*prcm)->cm_l4per_gptimer10_clkctrl,
  375. (*prcm)->cm_l4per_gptimer11_clkctrl,
  376. (*prcm)->cm_l4per_gptimer3_clkctrl,
  377. (*prcm)->cm_l4per_gptimer4_clkctrl,
  378. (*prcm)->cm_l4per_hdq1w_clkctrl,
  379. (*prcm)->cm_l4per_mcbsp4_clkctrl,
  380. (*prcm)->cm_l4per_mcspi2_clkctrl,
  381. (*prcm)->cm_l4per_mcspi3_clkctrl,
  382. (*prcm)->cm_l4per_mcspi4_clkctrl,
  383. (*prcm)->cm_l4per_mmcsd3_clkctrl,
  384. (*prcm)->cm_l4per_mmcsd4_clkctrl,
  385. (*prcm)->cm_l4per_mmcsd5_clkctrl,
  386. (*prcm)->cm_l4per_uart1_clkctrl,
  387. (*prcm)->cm_l4per_uart2_clkctrl,
  388. (*prcm)->cm_l4per_uart4_clkctrl,
  389. (*prcm)->cm_wkup_keyboard_clkctrl,
  390. (*prcm)->cm_wkup_wdtimer2_clkctrl,
  391. (*prcm)->cm_cam_iss_clkctrl,
  392. (*prcm)->cm_cam_fdif_clkctrl,
  393. (*prcm)->cm_dss_dss_clkctrl,
  394. (*prcm)->cm_sgx_sgx_clkctrl,
  395. 0
  396. };
  397. /* Enable optional functional clock for ISS */
  398. setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
  399. /* Enable all optional functional clocks of DSS */
  400. setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
  401. do_enable_clocks(clk_domains_non_essential,
  402. clk_modules_hw_auto_non_essential,
  403. clk_modules_explicit_en_non_essential,
  404. 0);
  405. /* Put camera module in no sleep mode */
  406. clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
  407. MODULE_CLKCTRL_MODULEMODE_MASK,
  408. CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
  409. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  410. }
  411. void hw_data_init(void)
  412. {
  413. u32 omap_rev = omap_revision();
  414. (*prcm) = &omap4_prcm;
  415. switch (omap_rev) {
  416. case OMAP4430_ES1_0:
  417. *dplls_data = &omap4430_dplls_es1;
  418. *omap_vcores = &omap4430_volts_es1;
  419. break;
  420. case OMAP4430_ES2_0:
  421. case OMAP4430_ES2_1:
  422. case OMAP4430_ES2_2:
  423. case OMAP4430_ES2_3:
  424. *dplls_data = &omap4430_dplls;
  425. *omap_vcores = &omap4430_volts;
  426. break;
  427. case OMAP4460_ES1_0:
  428. case OMAP4460_ES1_1:
  429. *dplls_data = &omap4460_dplls;
  430. *omap_vcores = &omap4460_volts;
  431. break;
  432. default:
  433. printf("\n INVALID OMAP REVISION ");
  434. }
  435. *ctrl = &omap4_ctrl;
  436. }