board.c 13 KB

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  1. /*
  2. *
  3. * Common board functions for OMAP3 based boards.
  4. *
  5. * (C) Copyright 2004-2008
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Author :
  9. * Sunil Kumar <sunilsaini05@gmail.com>
  10. * Shashi Ranjan <shashiranjanmca05@gmail.com>
  11. *
  12. * Derived from Beagle Board and 3430 SDP code by
  13. * Richard Woodruff <r-woodruff2@ti.com>
  14. * Syed Mohammed Khasim <khasim@ti.com>
  15. *
  16. *
  17. * See file CREDITS for list of people who contributed to this
  18. * project.
  19. *
  20. * This program is free software; you can redistribute it and/or
  21. * modify it under the terms of the GNU General Public License as
  22. * published by the Free Software Foundation; either version 2 of
  23. * the License, or (at your option) any later version.
  24. *
  25. * This program is distributed in the hope that it will be useful,
  26. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28. * GNU General Public License for more details.
  29. *
  30. * You should have received a copy of the GNU General Public License
  31. * along with this program; if not, write to the Free Software
  32. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33. * MA 02111-1307 USA
  34. */
  35. #include <common.h>
  36. #include <spl.h>
  37. #include <asm/io.h>
  38. #include <asm/arch/sys_proto.h>
  39. #include <asm/arch/mem.h>
  40. #include <asm/cache.h>
  41. #include <asm/armv7.h>
  42. #include <asm/arch/gpio.h>
  43. #include <asm/omap_common.h>
  44. #include <asm/arch/mmc_host_def.h>
  45. #include <i2c.h>
  46. #include <linux/compiler.h>
  47. DECLARE_GLOBAL_DATA_PTR;
  48. /* Declarations */
  49. extern omap3_sysinfo sysinfo;
  50. static void omap3_setup_aux_cr(void);
  51. #ifndef CONFIG_SYS_L2CACHE_OFF
  52. static void omap3_invalidate_l2_cache_secure(void);
  53. #endif
  54. static const struct gpio_bank gpio_bank_34xx[6] = {
  55. { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
  56. { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
  57. { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
  58. { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
  59. { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
  60. { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
  61. };
  62. const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
  63. #ifdef CONFIG_SPL_BUILD
  64. /*
  65. * We use static variables because global data is not ready yet.
  66. * Initialized data is available in SPL right from the beginning.
  67. * We would not typically need to save these parameters in regular
  68. * U-Boot. This is needed only in SPL at the moment.
  69. */
  70. u32 omap3_boot_device = BOOT_DEVICE_NAND;
  71. /* auto boot mode detection is not possible for OMAP3 - hard code */
  72. u32 spl_boot_mode(void)
  73. {
  74. switch (spl_boot_device()) {
  75. case BOOT_DEVICE_MMC2:
  76. return MMCSD_MODE_RAW;
  77. case BOOT_DEVICE_MMC1:
  78. return MMCSD_MODE_FAT;
  79. break;
  80. default:
  81. puts("spl: ERROR: unknown device - can't select boot mode\n");
  82. hang();
  83. }
  84. }
  85. u32 spl_boot_device(void)
  86. {
  87. return omap3_boot_device;
  88. }
  89. int board_mmc_init(bd_t *bis)
  90. {
  91. switch (spl_boot_device()) {
  92. case BOOT_DEVICE_MMC1:
  93. omap_mmc_init(0, 0, 0, -1, -1);
  94. break;
  95. case BOOT_DEVICE_MMC2:
  96. case BOOT_DEVICE_MMC2_2:
  97. omap_mmc_init(1, 0, 0, -1, -1);
  98. break;
  99. }
  100. return 0;
  101. }
  102. void spl_board_init(void)
  103. {
  104. #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
  105. gpmc_init();
  106. #endif
  107. #ifdef CONFIG_SPL_I2C_SUPPORT
  108. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  109. #endif
  110. }
  111. #endif /* CONFIG_SPL_BUILD */
  112. /******************************************************************************
  113. * Routine: secure_unlock
  114. * Description: Setup security registers for access
  115. * (GP Device only)
  116. *****************************************************************************/
  117. void secure_unlock_mem(void)
  118. {
  119. struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
  120. struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
  121. struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
  122. struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
  123. struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
  124. /* Protection Module Register Target APE (PM_RT) */
  125. writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
  126. writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
  127. writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
  128. writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
  129. writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
  130. writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
  131. writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
  132. writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
  133. writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
  134. writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
  135. writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
  136. /* IVA Changes */
  137. writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
  138. writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
  139. writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
  140. /* SDRC region 0 public */
  141. writel(UNLOCK_1, &sms_base->rg_att0);
  142. }
  143. /******************************************************************************
  144. * Routine: secureworld_exit()
  145. * Description: If chip is EMU and boot type is external
  146. * configure secure registers and exit secure world
  147. * general use.
  148. *****************************************************************************/
  149. void secureworld_exit()
  150. {
  151. unsigned long i;
  152. /* configure non-secure access control register */
  153. __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
  154. /* enabling co-processor CP10 and CP11 accesses in NS world */
  155. __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
  156. /*
  157. * allow allocation of locked TLBs and L2 lines in NS world
  158. * allow use of PLE registers in NS world also
  159. */
  160. __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
  161. __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
  162. /* Enable ASA in ACR register */
  163. __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
  164. __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
  165. __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
  166. /* Exiting secure world */
  167. __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
  168. __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
  169. __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
  170. }
  171. /******************************************************************************
  172. * Routine: try_unlock_sram()
  173. * Description: If chip is GP/EMU(special) type, unlock the SRAM for
  174. * general use.
  175. *****************************************************************************/
  176. void try_unlock_memory()
  177. {
  178. int mode;
  179. int in_sdram = is_running_in_sdram();
  180. /*
  181. * if GP device unlock device SRAM for general use
  182. * secure code breaks for Secure/Emulation device - HS/E/T
  183. */
  184. mode = get_device_type();
  185. if (mode == GP_DEVICE)
  186. secure_unlock_mem();
  187. /*
  188. * If device is EMU and boot is XIP external booting
  189. * Unlock firewalls and disable L2 and put chip
  190. * out of secure world
  191. *
  192. * Assuming memories are unlocked by the demon who put us in SDRAM
  193. */
  194. if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
  195. && (!in_sdram)) {
  196. secure_unlock_mem();
  197. secureworld_exit();
  198. }
  199. return;
  200. }
  201. /******************************************************************************
  202. * Routine: s_init
  203. * Description: Does early system init of muxing and clocks.
  204. * - Called path is with SRAM stack.
  205. *****************************************************************************/
  206. void s_init(void)
  207. {
  208. int in_sdram = is_running_in_sdram();
  209. watchdog_init();
  210. try_unlock_memory();
  211. /* Errata workarounds */
  212. omap3_setup_aux_cr();
  213. #ifndef CONFIG_SYS_L2CACHE_OFF
  214. /* Invalidate L2-cache from secure mode */
  215. omap3_invalidate_l2_cache_secure();
  216. #endif
  217. set_muxconf_regs();
  218. sdelay(100);
  219. prcm_init();
  220. per_clocks_enable();
  221. #ifdef CONFIG_USB_EHCI_OMAP
  222. ehci_clocks_enable();
  223. #endif
  224. #ifdef CONFIG_SPL_BUILD
  225. gd = &gdata;
  226. preloader_console_init();
  227. timer_init();
  228. #endif
  229. if (!in_sdram)
  230. mem_init();
  231. }
  232. /*
  233. * Routine: misc_init_r
  234. * Description: A basic misc_init_r that just displays the die ID
  235. */
  236. int __weak misc_init_r(void)
  237. {
  238. dieid_num_r();
  239. return 0;
  240. }
  241. /******************************************************************************
  242. * Routine: wait_for_command_complete
  243. * Description: Wait for posting to finish on watchdog
  244. *****************************************************************************/
  245. void wait_for_command_complete(struct watchdog *wd_base)
  246. {
  247. int pending = 1;
  248. do {
  249. pending = readl(&wd_base->wwps);
  250. } while (pending);
  251. }
  252. /******************************************************************************
  253. * Routine: watchdog_init
  254. * Description: Shut down watch dogs
  255. *****************************************************************************/
  256. void watchdog_init(void)
  257. {
  258. struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
  259. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  260. /*
  261. * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
  262. * either taken care of by ROM (HS/EMU) or not accessible (GP).
  263. * We need to take care of WD2-MPU or take a PRCM reset. WD3
  264. * should not be running and does not generate a PRCM reset.
  265. */
  266. sr32(&prcm_base->fclken_wkup, 5, 1, 1);
  267. sr32(&prcm_base->iclken_wkup, 5, 1, 1);
  268. wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
  269. writel(WD_UNLOCK1, &wd2_base->wspr);
  270. wait_for_command_complete(wd2_base);
  271. writel(WD_UNLOCK2, &wd2_base->wspr);
  272. }
  273. /******************************************************************************
  274. * Dummy function to handle errors for EABI incompatibility
  275. *****************************************************************************/
  276. void abort(void)
  277. {
  278. }
  279. #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
  280. /******************************************************************************
  281. * OMAP3 specific command to switch between NAND HW and SW ecc
  282. *****************************************************************************/
  283. static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
  284. {
  285. if (argc != 2)
  286. goto usage;
  287. if (strncmp(argv[1], "hw", 2) == 0)
  288. omap_nand_switch_ecc(1);
  289. else if (strncmp(argv[1], "sw", 2) == 0)
  290. omap_nand_switch_ecc(0);
  291. else
  292. goto usage;
  293. return 0;
  294. usage:
  295. printf ("Usage: nandecc %s\n", cmdtp->usage);
  296. return 1;
  297. }
  298. U_BOOT_CMD(
  299. nandecc, 2, 1, do_switch_ecc,
  300. "switch OMAP3 NAND ECC calculation algorithm",
  301. "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
  302. );
  303. #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
  304. #ifdef CONFIG_DISPLAY_BOARDINFO
  305. /**
  306. * Print board information
  307. */
  308. int checkboard (void)
  309. {
  310. char *mem_s ;
  311. if (is_mem_sdr())
  312. mem_s = "mSDR";
  313. else
  314. mem_s = "LPDDR";
  315. printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
  316. sysinfo.nand_string);
  317. return 0;
  318. }
  319. #endif /* CONFIG_DISPLAY_BOARDINFO */
  320. static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
  321. {
  322. u32 i, num_params = *parameters;
  323. u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
  324. /*
  325. * copy the parameters to an un-cached area to avoid coherency
  326. * issues
  327. */
  328. for (i = 0; i < num_params; i++) {
  329. __raw_writel(*parameters, sram_scratch_space);
  330. parameters++;
  331. sram_scratch_space++;
  332. }
  333. /* Now make the PPA call */
  334. do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
  335. }
  336. static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
  337. {
  338. u32 acr;
  339. /* Read ACR */
  340. asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
  341. acr &= ~clear_bits;
  342. acr |= set_bits;
  343. if (get_device_type() == GP_DEVICE) {
  344. omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
  345. acr);
  346. } else {
  347. struct emu_hal_params emu_romcode_params;
  348. emu_romcode_params.num_params = 1;
  349. emu_romcode_params.param1 = acr;
  350. omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
  351. (u32 *)&emu_romcode_params);
  352. }
  353. }
  354. static void omap3_setup_aux_cr(void)
  355. {
  356. /* Workaround for Cortex-A8 errata: #454179 #430973
  357. * Set "IBE" bit
  358. * Set "Disable Branch Size Mispredicts" bit
  359. * Workaround for erratum #621766
  360. * Enable L1NEON bit
  361. * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
  362. */
  363. omap3_update_aux_cr_secure(0xE0, 0);
  364. }
  365. #ifndef CONFIG_SYS_L2CACHE_OFF
  366. static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
  367. {
  368. u32 acr;
  369. /* Read ACR */
  370. asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
  371. acr &= ~clear_bits;
  372. acr |= set_bits;
  373. /* Write ACR - affects non-secure banked bits */
  374. asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
  375. }
  376. /* Invalidate the entire L2 cache from secure mode */
  377. static void omap3_invalidate_l2_cache_secure(void)
  378. {
  379. if (get_device_type() == GP_DEVICE) {
  380. omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
  381. 0);
  382. } else {
  383. struct emu_hal_params emu_romcode_params;
  384. emu_romcode_params.num_params = 1;
  385. emu_romcode_params.param1 = 0;
  386. omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
  387. (u32 *)&emu_romcode_params);
  388. }
  389. }
  390. void v7_outer_cache_enable(void)
  391. {
  392. /* Set L2EN */
  393. omap3_update_aux_cr_secure(0x2, 0);
  394. /*
  395. * On some revisions L2EN bit is banked on some revisions it's not
  396. * No harm in setting both banked bits(in fact this is required
  397. * by an erratum)
  398. */
  399. omap3_update_aux_cr(0x2, 0);
  400. }
  401. void omap3_outer_cache_disable(void)
  402. {
  403. /* Clear L2EN */
  404. omap3_update_aux_cr_secure(0, 0x2);
  405. /*
  406. * On some revisions L2EN bit is banked on some revisions it's not
  407. * No harm in clearing both banked bits(in fact this is required
  408. * by an erratum)
  409. */
  410. omap3_update_aux_cr(0, 0x2);
  411. }
  412. #endif /* !CONFIG_SYS_L2CACHE_OFF */
  413. #ifndef CONFIG_SYS_DCACHE_OFF
  414. void enable_caches(void)
  415. {
  416. /* Enable D-cache. I-cache is already enabled in start.S */
  417. dcache_enable();
  418. }
  419. #endif /* !CONFIG_SYS_DCACHE_OFF */