hwinit-common.c 5.9 KB

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  1. /*
  2. *
  3. * Common functions for OMAP4/5 based boards
  4. *
  5. * (C) Copyright 2010
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Author :
  9. * Aneesh V <aneesh@ti.com>
  10. * Steve Sakoman <steve@sakoman.com>
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. #include <common.h>
  31. #include <spl.h>
  32. #include <asm/arch/sys_proto.h>
  33. #include <asm/sizes.h>
  34. #include <asm/emif.h>
  35. #include <asm/omap_common.h>
  36. #include <linux/compiler.h>
  37. DECLARE_GLOBAL_DATA_PTR;
  38. void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
  39. {
  40. int i;
  41. struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
  42. for (i = 0; i < size; i++, pad++)
  43. writew(pad->val, base + pad->offset);
  44. }
  45. static void set_mux_conf_regs(void)
  46. {
  47. switch (omap_hw_init_context()) {
  48. case OMAP_INIT_CONTEXT_SPL:
  49. set_muxconf_regs_essential();
  50. break;
  51. case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
  52. #ifdef CONFIG_SYS_ENABLE_PADS_ALL
  53. set_muxconf_regs_non_essential();
  54. #endif
  55. break;
  56. case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
  57. case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
  58. set_muxconf_regs_essential();
  59. #ifdef CONFIG_SYS_ENABLE_PADS_ALL
  60. set_muxconf_regs_non_essential();
  61. #endif
  62. break;
  63. }
  64. }
  65. u32 cortex_rev(void)
  66. {
  67. unsigned int rev;
  68. /* Read Main ID Register (MIDR) */
  69. asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
  70. return rev;
  71. }
  72. void omap_rev_string(void)
  73. {
  74. u32 omap_rev = omap_revision();
  75. u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
  76. u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
  77. u32 major_rev = (omap_rev & 0x00000F00) >> 8;
  78. u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
  79. if (soc_variant)
  80. printf("OMAP");
  81. else
  82. printf("DRA");
  83. printf("%x ES%x.%x\n", omap_variant, major_rev,
  84. minor_rev);
  85. }
  86. #ifdef CONFIG_SPL_BUILD
  87. static void init_boot_params(void)
  88. {
  89. boot_params_ptr = (u32 *) &boot_params;
  90. }
  91. void spl_display_print(void)
  92. {
  93. omap_rev_string();
  94. }
  95. #endif
  96. void __weak srcomp_enable(void)
  97. {
  98. }
  99. /*
  100. * Routine: s_init
  101. * Description: Does early system init of watchdog, muxing, andclocks
  102. * Watchdog disable is done always. For the rest what gets done
  103. * depends on the boot mode in which this function is executed
  104. * 1. s_init of SPL running from SRAM
  105. * 2. s_init of U-Boot running from FLASH
  106. * 3. s_init of U-Boot loaded to SDRAM by SPL
  107. * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
  108. * Configuration Header feature
  109. * Please have a look at the respective functions to see what gets
  110. * done in each of these cases
  111. * This function is called with SRAM stack.
  112. */
  113. void s_init(void)
  114. {
  115. init_omap_revision();
  116. hw_data_init();
  117. #ifdef CONFIG_SPL_BUILD
  118. if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
  119. force_emif_self_refresh();
  120. #endif
  121. watchdog_init();
  122. set_mux_conf_regs();
  123. #ifdef CONFIG_SPL_BUILD
  124. srcomp_enable();
  125. setup_clocks_for_console();
  126. gd = &gdata;
  127. preloader_console_init();
  128. do_io_settings();
  129. #endif
  130. prcm_init();
  131. #ifdef CONFIG_SPL_BUILD
  132. timer_init();
  133. /* For regular u-boot sdram_init() is called from dram_init() */
  134. sdram_init();
  135. init_boot_params();
  136. #endif
  137. }
  138. /*
  139. * Routine: wait_for_command_complete
  140. * Description: Wait for posting to finish on watchdog
  141. */
  142. void wait_for_command_complete(struct watchdog *wd_base)
  143. {
  144. int pending = 1;
  145. do {
  146. pending = readl(&wd_base->wwps);
  147. } while (pending);
  148. }
  149. /*
  150. * Routine: watchdog_init
  151. * Description: Shut down watch dogs
  152. */
  153. void watchdog_init(void)
  154. {
  155. struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
  156. writel(WD_UNLOCK1, &wd2_base->wspr);
  157. wait_for_command_complete(wd2_base);
  158. writel(WD_UNLOCK2, &wd2_base->wspr);
  159. }
  160. /*
  161. * This function finds the SDRAM size available in the system
  162. * based on DMM section configurations
  163. * This is needed because the size of memory installed may be
  164. * different on different versions of the board
  165. */
  166. u32 omap_sdram_size(void)
  167. {
  168. u32 section, i, valid;
  169. u64 sdram_start = 0, sdram_end = 0, addr,
  170. size, total_size = 0, trap_size = 0;
  171. for (i = 0; i < 4; i++) {
  172. section = __raw_readl(DMM_BASE + i*4);
  173. valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
  174. (EMIF_SDRC_ADDRSPC_SHIFT);
  175. addr = section & EMIF_SYS_ADDR_MASK;
  176. /* See if the address is valid */
  177. if ((addr >= DRAM_ADDR_SPACE_START) &&
  178. (addr < DRAM_ADDR_SPACE_END)) {
  179. size = ((section & EMIF_SYS_SIZE_MASK) >>
  180. EMIF_SYS_SIZE_SHIFT);
  181. size = 1 << size;
  182. size *= SZ_16M;
  183. if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
  184. if (!sdram_start || (addr < sdram_start))
  185. sdram_start = addr;
  186. if (!sdram_end || ((addr + size) > sdram_end))
  187. sdram_end = addr + size;
  188. } else {
  189. trap_size = size;
  190. }
  191. }
  192. }
  193. total_size = (sdram_end - sdram_start) - (trap_size);
  194. return total_size;
  195. }
  196. /*
  197. * Routine: dram_init
  198. * Description: sets uboots idea of sdram size
  199. */
  200. int dram_init(void)
  201. {
  202. sdram_init();
  203. gd->ram_size = omap_sdram_size();
  204. return 0;
  205. }
  206. /*
  207. * Print board information
  208. */
  209. int checkboard(void)
  210. {
  211. puts(sysinfo.board_string);
  212. return 0;
  213. }
  214. /*
  215. * get_device_type(): tell if GP/HS/EMU/TST
  216. */
  217. u32 get_device_type(void)
  218. {
  219. return (readl((*ctrl)->control_status) &
  220. (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
  221. }
  222. /*
  223. * Print CPU information
  224. */
  225. int print_cpuinfo(void)
  226. {
  227. puts("CPU : ");
  228. omap_rev_string();
  229. return 0;
  230. }
  231. #ifndef CONFIG_SYS_DCACHE_OFF
  232. void enable_caches(void)
  233. {
  234. /* Enable D-cache. I-cache is already enabled in start.S */
  235. dcache_enable();
  236. }
  237. #endif