clocks-common.c 20 KB

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  1. /*
  2. *
  3. * Clock initialization for OMAP4
  4. *
  5. * (C) Copyright 2010
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Aneesh V <aneesh@ti.com>
  9. *
  10. * Based on previous work by:
  11. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  12. * Rajendra Nayak <rnayak@ti.com>
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. */
  32. #include <common.h>
  33. #include <asm/omap_common.h>
  34. #include <asm/gpio.h>
  35. #include <asm/arch/clocks.h>
  36. #include <asm/arch/sys_proto.h>
  37. #include <asm/utils.h>
  38. #include <asm/omap_gpio.h>
  39. #include <asm/emif.h>
  40. #ifndef CONFIG_SPL_BUILD
  41. /*
  42. * printing to console doesn't work unless
  43. * this code is executed from SPL
  44. */
  45. #define printf(fmt, args...)
  46. #define puts(s)
  47. #endif
  48. const u32 sys_clk_array[8] = {
  49. 12000000, /* 12 MHz */
  50. 13000000, /* 13 MHz */
  51. 16800000, /* 16.8 MHz */
  52. 19200000, /* 19.2 MHz */
  53. 26000000, /* 26 MHz */
  54. 27000000, /* 27 MHz */
  55. 38400000, /* 38.4 MHz */
  56. 20000000, /* 20 MHz */
  57. };
  58. static inline u32 __get_sys_clk_index(void)
  59. {
  60. s8 ind;
  61. /*
  62. * For ES1 the ROM code calibration of sys clock is not reliable
  63. * due to hw issue. So, use hard-coded value. If this value is not
  64. * correct for any board over-ride this function in board file
  65. * From ES2.0 onwards you will get this information from
  66. * CM_SYS_CLKSEL
  67. */
  68. if (omap_revision() == OMAP4430_ES1_0)
  69. ind = OMAP_SYS_CLK_IND_38_4_MHZ;
  70. else {
  71. /* SYS_CLKSEL - 1 to match the dpll param array indices */
  72. ind = (readl((*prcm)->cm_sys_clksel) &
  73. CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
  74. /*
  75. * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
  76. * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
  77. * NUM_SYS_CLK. So considering the last 3 bits as the index
  78. * for the dpll param array.
  79. */
  80. ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
  81. }
  82. return ind;
  83. }
  84. u32 get_sys_clk_index(void)
  85. __attribute__ ((weak, alias("__get_sys_clk_index")));
  86. u32 get_sys_clk_freq(void)
  87. {
  88. u8 index = get_sys_clk_index();
  89. return sys_clk_array[index];
  90. }
  91. void setup_post_dividers(u32 const base, const struct dpll_params *params)
  92. {
  93. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  94. /* Setup post-dividers */
  95. if (params->m2 >= 0)
  96. writel(params->m2, &dpll_regs->cm_div_m2_dpll);
  97. if (params->m3 >= 0)
  98. writel(params->m3, &dpll_regs->cm_div_m3_dpll);
  99. if (params->m4_h11 >= 0)
  100. writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
  101. if (params->m5_h12 >= 0)
  102. writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
  103. if (params->m6_h13 >= 0)
  104. writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
  105. if (params->m7_h14 >= 0)
  106. writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
  107. if (params->h21 >= 0)
  108. writel(params->h21, &dpll_regs->cm_div_h21_dpll);
  109. if (params->h22 >= 0)
  110. writel(params->h22, &dpll_regs->cm_div_h22_dpll);
  111. if (params->h23 >= 0)
  112. writel(params->h23, &dpll_regs->cm_div_h23_dpll);
  113. if (params->h24 >= 0)
  114. writel(params->h24, &dpll_regs->cm_div_h24_dpll);
  115. }
  116. static inline void do_bypass_dpll(u32 const base)
  117. {
  118. struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
  119. clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
  120. CM_CLKMODE_DPLL_DPLL_EN_MASK,
  121. DPLL_EN_FAST_RELOCK_BYPASS <<
  122. CM_CLKMODE_DPLL_EN_SHIFT);
  123. }
  124. static inline void wait_for_bypass(u32 const base)
  125. {
  126. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  127. if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
  128. LDELAY)) {
  129. printf("Bypassing DPLL failed %x\n", base);
  130. }
  131. }
  132. static inline void do_lock_dpll(u32 const base)
  133. {
  134. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  135. clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
  136. CM_CLKMODE_DPLL_DPLL_EN_MASK,
  137. DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
  138. }
  139. static inline void wait_for_lock(u32 const base)
  140. {
  141. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  142. if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
  143. &dpll_regs->cm_idlest_dpll, LDELAY)) {
  144. printf("DPLL locking failed for %x\n", base);
  145. hang();
  146. }
  147. }
  148. inline u32 check_for_lock(u32 const base)
  149. {
  150. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  151. u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
  152. return lock;
  153. }
  154. const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
  155. {
  156. u32 sysclk_ind = get_sys_clk_index();
  157. return &dpll_data->mpu[sysclk_ind];
  158. }
  159. const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
  160. {
  161. u32 sysclk_ind = get_sys_clk_index();
  162. return &dpll_data->core[sysclk_ind];
  163. }
  164. const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
  165. {
  166. u32 sysclk_ind = get_sys_clk_index();
  167. return &dpll_data->per[sysclk_ind];
  168. }
  169. const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
  170. {
  171. u32 sysclk_ind = get_sys_clk_index();
  172. return &dpll_data->iva[sysclk_ind];
  173. }
  174. const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
  175. {
  176. u32 sysclk_ind = get_sys_clk_index();
  177. return &dpll_data->usb[sysclk_ind];
  178. }
  179. const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
  180. {
  181. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  182. u32 sysclk_ind = get_sys_clk_index();
  183. return &dpll_data->abe[sysclk_ind];
  184. #else
  185. return dpll_data->abe;
  186. #endif
  187. }
  188. static const struct dpll_params *get_ddr_dpll_params
  189. (struct dplls const *dpll_data)
  190. {
  191. u32 sysclk_ind = get_sys_clk_index();
  192. if (!dpll_data->ddr)
  193. return NULL;
  194. return &dpll_data->ddr[sysclk_ind];
  195. }
  196. static void do_setup_dpll(u32 const base, const struct dpll_params *params,
  197. u8 lock, char *dpll)
  198. {
  199. u32 temp, M, N;
  200. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  201. if (!params)
  202. return;
  203. temp = readl(&dpll_regs->cm_clksel_dpll);
  204. if (check_for_lock(base)) {
  205. /*
  206. * The Dpll has already been locked by rom code using CH.
  207. * Check if M,N are matching with Ideal nominal opp values.
  208. * If matches, skip the rest otherwise relock.
  209. */
  210. M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
  211. N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
  212. if ((M != (params->m)) || (N != (params->n))) {
  213. debug("\n %s Dpll locked, but not for ideal M = %d,"
  214. "N = %d values, current values are M = %d,"
  215. "N= %d" , dpll, params->m, params->n,
  216. M, N);
  217. } else {
  218. /* Dpll locked with ideal values for nominal opps. */
  219. debug("\n %s Dpll already locked with ideal"
  220. "nominal opp values", dpll);
  221. goto setup_post_dividers;
  222. }
  223. }
  224. bypass_dpll(base);
  225. /* Set M & N */
  226. temp &= ~CM_CLKSEL_DPLL_M_MASK;
  227. temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
  228. temp &= ~CM_CLKSEL_DPLL_N_MASK;
  229. temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
  230. writel(temp, &dpll_regs->cm_clksel_dpll);
  231. /* Lock */
  232. if (lock)
  233. do_lock_dpll(base);
  234. setup_post_dividers:
  235. setup_post_dividers(base, params);
  236. /* Wait till the DPLL locks */
  237. if (lock)
  238. wait_for_lock(base);
  239. }
  240. u32 omap_ddr_clk(void)
  241. {
  242. u32 ddr_clk, sys_clk_khz, omap_rev, divider;
  243. const struct dpll_params *core_dpll_params;
  244. omap_rev = omap_revision();
  245. sys_clk_khz = get_sys_clk_freq() / 1000;
  246. core_dpll_params = get_core_dpll_params(*dplls_data);
  247. debug("sys_clk %d\n ", sys_clk_khz * 1000);
  248. /* Find Core DPLL locked frequency first */
  249. ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
  250. (core_dpll_params->n + 1);
  251. if (omap_rev < OMAP5430_ES1_0) {
  252. /*
  253. * DDR frequency is PHY_ROOT_CLK/2
  254. * PHY_ROOT_CLK = Fdpll/2/M2
  255. */
  256. divider = 4;
  257. } else {
  258. /*
  259. * DDR frequency is PHY_ROOT_CLK
  260. * PHY_ROOT_CLK = Fdpll/2/M2
  261. */
  262. divider = 2;
  263. }
  264. ddr_clk = ddr_clk / divider / core_dpll_params->m2;
  265. ddr_clk *= 1000; /* convert to Hz */
  266. debug("ddr_clk %d\n ", ddr_clk);
  267. return ddr_clk;
  268. }
  269. /*
  270. * Lock MPU dpll
  271. *
  272. * Resulting MPU frequencies:
  273. * 4430 ES1.0 : 600 MHz
  274. * 4430 ES2.x : 792 MHz (OPP Turbo)
  275. * 4460 : 920 MHz (OPP Turbo) - DCC disabled
  276. */
  277. void configure_mpu_dpll(void)
  278. {
  279. const struct dpll_params *params;
  280. struct dpll_regs *mpu_dpll_regs;
  281. u32 omap_rev;
  282. omap_rev = omap_revision();
  283. /*
  284. * DCC and clock divider settings for 4460.
  285. * DCC is required, if more than a certain frequency is required.
  286. * For, 4460 > 1GHZ.
  287. * 5430 > 1.4GHZ.
  288. */
  289. if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
  290. mpu_dpll_regs =
  291. (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
  292. bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
  293. clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
  294. MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
  295. setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
  296. MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
  297. clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
  298. CM_CLKSEL_DCC_EN_MASK);
  299. }
  300. params = get_mpu_dpll_params(*dplls_data);
  301. do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
  302. debug("MPU DPLL locked\n");
  303. }
  304. #ifdef CONFIG_USB_EHCI_OMAP
  305. static void setup_usb_dpll(void)
  306. {
  307. const struct dpll_params *params;
  308. u32 sys_clk_khz, sd_div, num, den;
  309. sys_clk_khz = get_sys_clk_freq() / 1000;
  310. /*
  311. * USB:
  312. * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
  313. * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
  314. * - where CLKINP is sys_clk in MHz
  315. * Use CLKINP in KHz and adjust the denominator accordingly so
  316. * that we have enough accuracy and at the same time no overflow
  317. */
  318. params = get_usb_dpll_params(*dplls_data);
  319. num = params->m * sys_clk_khz;
  320. den = (params->n + 1) * 250 * 1000;
  321. num += den - 1;
  322. sd_div = num / den;
  323. clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
  324. CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
  325. sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
  326. /* Now setup the dpll with the regular function */
  327. do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
  328. }
  329. #endif
  330. static void setup_dplls(void)
  331. {
  332. u32 temp;
  333. const struct dpll_params *params;
  334. debug("setup_dplls\n");
  335. /* CORE dpll */
  336. params = get_core_dpll_params(*dplls_data); /* default - safest */
  337. /*
  338. * Do not lock the core DPLL now. Just set it up.
  339. * Core DPLL will be locked after setting up EMIF
  340. * using the FREQ_UPDATE method(freq_update_core())
  341. */
  342. if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
  343. do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
  344. DPLL_NO_LOCK, "core");
  345. else
  346. do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
  347. DPLL_LOCK, "core");
  348. /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
  349. temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
  350. (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
  351. (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
  352. writel(temp, (*prcm)->cm_clksel_core);
  353. debug("Core DPLL configured\n");
  354. /* lock PER dpll */
  355. params = get_per_dpll_params(*dplls_data);
  356. do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
  357. params, DPLL_LOCK, "per");
  358. debug("PER DPLL locked\n");
  359. /* MPU dpll */
  360. configure_mpu_dpll();
  361. #ifdef CONFIG_USB_EHCI_OMAP
  362. setup_usb_dpll();
  363. #endif
  364. params = get_ddr_dpll_params(*dplls_data);
  365. do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
  366. params, DPLL_LOCK, "ddr");
  367. }
  368. #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
  369. static void setup_non_essential_dplls(void)
  370. {
  371. u32 abe_ref_clk;
  372. const struct dpll_params *params;
  373. /* IVA */
  374. clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
  375. CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
  376. params = get_iva_dpll_params(*dplls_data);
  377. do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
  378. /* Configure ABE dpll */
  379. params = get_abe_dpll_params(*dplls_data);
  380. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  381. abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
  382. #else
  383. abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
  384. /*
  385. * We need to enable some additional options to achieve
  386. * 196.608MHz from 32768 Hz
  387. */
  388. setbits_le32((*prcm)->cm_clkmode_dpll_abe,
  389. CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
  390. CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
  391. CM_CLKMODE_DPLL_LPMODE_EN_MASK|
  392. CM_CLKMODE_DPLL_REGM4XEN_MASK);
  393. /* Spend 4 REFCLK cycles at each stage */
  394. clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
  395. CM_CLKMODE_DPLL_RAMP_RATE_MASK,
  396. 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
  397. #endif
  398. /* Select the right reference clk */
  399. clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
  400. CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
  401. abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
  402. /* Lock the dpll */
  403. do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
  404. }
  405. #endif
  406. u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
  407. {
  408. u32 offset_code;
  409. volt_offset -= pmic->base_offset;
  410. offset_code = (volt_offset + pmic->step - 1) / pmic->step;
  411. /*
  412. * Offset codes 1-6 all give the base voltage in Palmas
  413. * Offset code 0 switches OFF the SMPS
  414. */
  415. return offset_code + pmic->start_code;
  416. }
  417. void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
  418. {
  419. u32 offset_code;
  420. u32 offset = volt_mv;
  421. int ret = 0;
  422. /* See if we can first get the GPIO if needed */
  423. if (pmic->gpio_en)
  424. ret = gpio_request(pmic->gpio, "PMIC_GPIO");
  425. if (ret < 0) {
  426. printf("%s: gpio %d request failed %d\n", __func__,
  427. pmic->gpio, ret);
  428. return;
  429. }
  430. /* Pull the GPIO low to select SET0 register, while we program SET1 */
  431. if (pmic->gpio_en)
  432. gpio_direction_output(pmic->gpio, 0);
  433. /* convert to uV for better accuracy in the calculations */
  434. offset *= 1000;
  435. offset_code = get_offset_code(offset, pmic);
  436. debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
  437. offset_code);
  438. if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
  439. vcore_reg, offset_code))
  440. printf("Scaling voltage failed for 0x%x\n", vcore_reg);
  441. if (pmic->gpio_en)
  442. gpio_direction_output(pmic->gpio, 1);
  443. }
  444. /*
  445. * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
  446. * We set the maximum voltages allowed here because Smart-Reflex is not
  447. * enabled in bootloader. Voltage initialization in the kernel will set
  448. * these to the nominal values after enabling Smart-Reflex
  449. */
  450. void scale_vcores(struct vcores_data const *vcores)
  451. {
  452. omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
  453. do_scale_vcore(vcores->core.addr, vcores->core.value,
  454. vcores->core.pmic);
  455. do_scale_vcore(vcores->mpu.addr, vcores->mpu.value,
  456. vcores->mpu.pmic);
  457. do_scale_vcore(vcores->mm.addr, vcores->mm.value,
  458. vcores->mm.pmic);
  459. if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
  460. /* Configure LDO SRAM "magic" bits */
  461. writel(2, (*prcm)->prm_sldo_core_setup);
  462. writel(2, (*prcm)->prm_sldo_mpu_setup);
  463. writel(2, (*prcm)->prm_sldo_mm_setup);
  464. }
  465. }
  466. static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
  467. {
  468. clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
  469. enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
  470. debug("Enable clock domain - %x\n", clkctrl_reg);
  471. }
  472. static inline void wait_for_clk_enable(u32 clkctrl_addr)
  473. {
  474. u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
  475. u32 bound = LDELAY;
  476. while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
  477. (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
  478. clkctrl = readl(clkctrl_addr);
  479. idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
  480. MODULE_CLKCTRL_IDLEST_SHIFT;
  481. if (--bound == 0) {
  482. printf("Clock enable failed for 0x%x idlest 0x%x\n",
  483. clkctrl_addr, clkctrl);
  484. return;
  485. }
  486. }
  487. }
  488. static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
  489. u32 wait_for_enable)
  490. {
  491. clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
  492. enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
  493. debug("Enable clock module - %x\n", clkctrl_addr);
  494. if (wait_for_enable)
  495. wait_for_clk_enable(clkctrl_addr);
  496. }
  497. void freq_update_core(void)
  498. {
  499. u32 freq_config1 = 0;
  500. const struct dpll_params *core_dpll_params;
  501. u32 omap_rev = omap_revision();
  502. core_dpll_params = get_core_dpll_params(*dplls_data);
  503. /* Put EMIF clock domain in sw wakeup mode */
  504. enable_clock_domain((*prcm)->cm_memif_clkstctrl,
  505. CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
  506. wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
  507. wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
  508. freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
  509. SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
  510. freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
  511. SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
  512. freq_config1 |= (core_dpll_params->m2 <<
  513. SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
  514. SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
  515. writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
  516. if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
  517. (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
  518. puts("FREQ UPDATE procedure failed!!");
  519. hang();
  520. }
  521. /*
  522. * Putting EMIF in HW_AUTO is seen to be causing issues with
  523. * EMIF clocks and the master DLL. Put EMIF in SW_WKUP
  524. * in OMAP5430 ES1.0 silicon
  525. */
  526. if (omap_rev != OMAP5430_ES1_0) {
  527. /* Put EMIF clock domain back in hw auto mode */
  528. enable_clock_domain((*prcm)->cm_memif_clkstctrl,
  529. CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
  530. wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
  531. wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
  532. }
  533. }
  534. void bypass_dpll(u32 const base)
  535. {
  536. do_bypass_dpll(base);
  537. wait_for_bypass(base);
  538. }
  539. void lock_dpll(u32 const base)
  540. {
  541. do_lock_dpll(base);
  542. wait_for_lock(base);
  543. }
  544. void setup_clocks_for_console(void)
  545. {
  546. /* Do not add any spl_debug prints in this function */
  547. clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  548. CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
  549. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  550. /* Enable all UARTs - console will be on one of them */
  551. clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
  552. MODULE_CLKCTRL_MODULEMODE_MASK,
  553. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  554. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  555. clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
  556. MODULE_CLKCTRL_MODULEMODE_MASK,
  557. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  558. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  559. clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
  560. MODULE_CLKCTRL_MODULEMODE_MASK,
  561. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  562. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  563. clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
  564. MODULE_CLKCTRL_MODULEMODE_MASK,
  565. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
  566. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  567. clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
  568. CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
  569. CD_CLKCTRL_CLKTRCTRL_SHIFT);
  570. }
  571. void do_enable_clocks(u32 const *clk_domains,
  572. u32 const *clk_modules_hw_auto,
  573. u32 const *clk_modules_explicit_en,
  574. u8 wait_for_enable)
  575. {
  576. u32 i, max = 100;
  577. /* Put the clock domains in SW_WKUP mode */
  578. for (i = 0; (i < max) && clk_domains[i]; i++) {
  579. enable_clock_domain(clk_domains[i],
  580. CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
  581. }
  582. /* Clock modules that need to be put in HW_AUTO */
  583. for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
  584. enable_clock_module(clk_modules_hw_auto[i],
  585. MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
  586. wait_for_enable);
  587. };
  588. /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
  589. for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
  590. enable_clock_module(clk_modules_explicit_en[i],
  591. MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
  592. wait_for_enable);
  593. };
  594. /* Put the clock domains in HW_AUTO mode now */
  595. for (i = 0; (i < max) && clk_domains[i]; i++) {
  596. enable_clock_domain(clk_domains[i],
  597. CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
  598. }
  599. }
  600. void prcm_init(void)
  601. {
  602. switch (omap_hw_init_context()) {
  603. case OMAP_INIT_CONTEXT_SPL:
  604. case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
  605. case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
  606. enable_basic_clocks();
  607. scale_vcores(*omap_vcores);
  608. setup_dplls();
  609. #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
  610. setup_non_essential_dplls();
  611. enable_non_essential_clocks();
  612. #endif
  613. break;
  614. default:
  615. break;
  616. }
  617. if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
  618. enable_basic_uboot_clocks();
  619. }