soc.c 5.5 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Sascha Hauer, Pengutronix
  4. *
  5. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <common.h>
  26. #include <asm/errno.h>
  27. #include <asm/io.h>
  28. #include <asm/arch/imx-regs.h>
  29. #include <asm/arch/clock.h>
  30. #include <asm/arch/sys_proto.h>
  31. #include <asm/imx-common/boot_mode.h>
  32. #include <stdbool.h>
  33. struct scu_regs {
  34. u32 ctrl;
  35. u32 config;
  36. u32 status;
  37. u32 invalidate;
  38. u32 fpga_rev;
  39. };
  40. u32 get_cpu_rev(void)
  41. {
  42. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  43. u32 reg = readl(&anatop->digprog_sololite);
  44. u32 type = ((reg >> 16) & 0xff);
  45. if (type != MXC_CPU_MX6SL) {
  46. reg = readl(&anatop->digprog);
  47. type = ((reg >> 16) & 0xff);
  48. if (type == MXC_CPU_MX6DL) {
  49. struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
  50. u32 cfg = readl(&scu->config) & 3;
  51. if (!cfg)
  52. type = MXC_CPU_MX6SOLO;
  53. }
  54. }
  55. reg &= 0xff; /* mx6 silicon revision */
  56. return (type << 12) | (reg + 0x10);
  57. }
  58. void init_aips(void)
  59. {
  60. struct aipstz_regs *aips1, *aips2;
  61. aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
  62. aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
  63. /*
  64. * Set all MPROTx to be non-bufferable, trusted for R/W,
  65. * not forced to user-mode.
  66. */
  67. writel(0x77777777, &aips1->mprot0);
  68. writel(0x77777777, &aips1->mprot1);
  69. writel(0x77777777, &aips2->mprot0);
  70. writel(0x77777777, &aips2->mprot1);
  71. /*
  72. * Set all OPACRx to be non-bufferable, not require
  73. * supervisor privilege level for access,allow for
  74. * write access and untrusted master access.
  75. */
  76. writel(0x00000000, &aips1->opacr0);
  77. writel(0x00000000, &aips1->opacr1);
  78. writel(0x00000000, &aips1->opacr2);
  79. writel(0x00000000, &aips1->opacr3);
  80. writel(0x00000000, &aips1->opacr4);
  81. writel(0x00000000, &aips2->opacr0);
  82. writel(0x00000000, &aips2->opacr1);
  83. writel(0x00000000, &aips2->opacr2);
  84. writel(0x00000000, &aips2->opacr3);
  85. writel(0x00000000, &aips2->opacr4);
  86. }
  87. /*
  88. * Set the VDDSOC
  89. *
  90. * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set
  91. * them to the specified millivolt level.
  92. * Possible values are from 0.725V to 1.450V in steps of
  93. * 0.025V (25mV).
  94. */
  95. void set_vddsoc(u32 mv)
  96. {
  97. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  98. u32 val, reg = readl(&anatop->reg_core);
  99. if (mv < 725)
  100. val = 0x00; /* Power gated off */
  101. else if (mv > 1450)
  102. val = 0x1F; /* Power FET switched full on. No regulation */
  103. else
  104. val = (mv - 700) / 25;
  105. /*
  106. * Mask out the REG_CORE[22:18] bits (REG2_TRIG)
  107. * and set them to the calculated value (0.7V + val * 0.25V)
  108. */
  109. reg = (reg & ~(0x1F << 18)) | (val << 18);
  110. writel(reg, &anatop->reg_core);
  111. }
  112. static void imx_set_wdog_powerdown(bool enable)
  113. {
  114. struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  115. struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  116. /* Write to the PDE (Power Down Enable) bit */
  117. writew(enable, &wdog1->wmcr);
  118. writew(enable, &wdog2->wmcr);
  119. }
  120. int arch_cpu_init(void)
  121. {
  122. init_aips();
  123. set_vddsoc(1200); /* Set VDDSOC to 1.2V */
  124. imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
  125. return 0;
  126. }
  127. #ifndef CONFIG_SYS_DCACHE_OFF
  128. void enable_caches(void)
  129. {
  130. /* Enable D-cache. I-cache is already enabled in start.S */
  131. dcache_enable();
  132. }
  133. #endif
  134. #if defined(CONFIG_FEC_MXC)
  135. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  136. {
  137. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  138. struct fuse_bank *bank = &iim->bank[4];
  139. struct fuse_bank4_regs *fuse =
  140. (struct fuse_bank4_regs *)bank->fuse_regs;
  141. u32 value = readl(&fuse->mac_addr_high);
  142. mac[0] = (value >> 8);
  143. mac[1] = value ;
  144. value = readl(&fuse->mac_addr_low);
  145. mac[2] = value >> 24 ;
  146. mac[3] = value >> 16 ;
  147. mac[4] = value >> 8 ;
  148. mac[5] = value ;
  149. }
  150. #endif
  151. void boot_mode_apply(unsigned cfg_val)
  152. {
  153. unsigned reg;
  154. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  155. writel(cfg_val, &psrc->gpr9);
  156. reg = readl(&psrc->gpr10);
  157. if (cfg_val)
  158. reg |= 1 << 28;
  159. else
  160. reg &= ~(1 << 28);
  161. writel(reg, &psrc->gpr10);
  162. }
  163. /*
  164. * cfg_val will be used for
  165. * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
  166. * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
  167. * to SBMR1, which will determine the boot device.
  168. */
  169. const struct boot_mode soc_boot_modes[] = {
  170. {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
  171. /* reserved value should start rom usb */
  172. {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
  173. {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
  174. {"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
  175. {"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
  176. {"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
  177. {"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
  178. /* 4 bit bus width */
  179. {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  180. {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  181. {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  182. {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  183. {NULL, 0},
  184. };
  185. void s_init(void)
  186. {
  187. }