ddr.c 3.8 KB

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  1. /*
  2. * DDR Configuration for AM33xx devices.
  3. *
  4. * Copyright (C) 2011 Texas Instruments Incorporated -
  5. http://www.ti.com/
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/ddr_defs.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/io.h>
  21. #include <asm/emif.h>
  22. /**
  23. * Base address for EMIF instances
  24. */
  25. static struct emif_reg_struct *emif_reg = {
  26. (struct emif_reg_struct *)EMIF4_0_CFG_BASE};
  27. /**
  28. * Base address for DDR instance
  29. */
  30. static struct ddr_regs *ddr_reg[2] = {
  31. (struct ddr_regs *)DDR_PHY_BASE_ADDR,
  32. (struct ddr_regs *)DDR_PHY_BASE_ADDR2};
  33. /**
  34. * Base address for ddr io control instances
  35. */
  36. static struct ddr_cmdtctrl *ioctrl_reg = {
  37. (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  38. /**
  39. * Configure SDRAM
  40. */
  41. void config_sdram(const struct emif_regs *regs)
  42. {
  43. if (regs->zq_config) {
  44. /*
  45. * A value of 0x2800 for the REF CTRL will give us
  46. * about 570us for a delay, which will be long enough
  47. * to configure things.
  48. */
  49. writel(0x2800, &emif_reg->emif_sdram_ref_ctrl);
  50. writel(regs->zq_config, &emif_reg->emif_zq_config);
  51. writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
  52. }
  53. writel(regs->sdram_config, &emif_reg->emif_sdram_config);
  54. writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
  55. writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
  56. }
  57. /**
  58. * Set SDRAM timings
  59. */
  60. void set_sdram_timings(const struct emif_regs *regs)
  61. {
  62. writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
  63. writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
  64. writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
  65. writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
  66. writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
  67. writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
  68. }
  69. /**
  70. * Configure DDR PHY
  71. */
  72. void config_ddr_phy(const struct emif_regs *regs)
  73. {
  74. writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
  75. writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
  76. }
  77. /**
  78. * Configure DDR CMD control registers
  79. */
  80. void config_cmd_ctrl(const struct cmd_control *cmd)
  81. {
  82. writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
  83. writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
  84. writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
  85. writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
  86. writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
  87. writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
  88. writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
  89. writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
  90. writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
  91. }
  92. /**
  93. * Configure DDR DATA registers
  94. */
  95. void config_ddr_data(int macrono, const struct ddr_data *data)
  96. {
  97. writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
  98. writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
  99. writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
  100. writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
  101. writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
  102. writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
  103. writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
  104. writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
  105. }
  106. void config_io_ctrl(unsigned long val)
  107. {
  108. writel(val, &ioctrl_reg->cm0ioctl);
  109. writel(val, &ioctrl_reg->cm1ioctl);
  110. writel(val, &ioctrl_reg->cm2ioctl);
  111. writel(val, &ioctrl_reg->dt0ioctl);
  112. writel(val, &ioctrl_reg->dt1ioctl);
  113. }