at91sam9x5_devices.c 7.4 KB

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  1. /*
  2. * Copyright (C) 2012 Atmel Corporation
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/arch/at91_common.h>
  24. #include <asm/arch/at91_pmc.h>
  25. #include <asm/arch/gpio.h>
  26. #include <asm/io.h>
  27. unsigned int get_chip_id(void)
  28. {
  29. /* The 0x40 is the offset of cidr in DBGU */
  30. return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
  31. }
  32. unsigned int get_extension_chip_id(void)
  33. {
  34. /* The 0x44 is the offset of exid in DBGU */
  35. return readl(ATMEL_BASE_DBGU + 0x44);
  36. }
  37. unsigned int has_emac1()
  38. {
  39. return cpu_is_at91sam9x25();
  40. }
  41. unsigned int has_emac0()
  42. {
  43. return !(cpu_is_at91sam9g15());
  44. }
  45. unsigned int has_lcdc()
  46. {
  47. return cpu_is_at91sam9g15() || cpu_is_at91sam9g35()
  48. || cpu_is_at91sam9x35();
  49. }
  50. char *get_cpu_name()
  51. {
  52. unsigned int extension_id = get_extension_chip_id();
  53. if (cpu_is_at91sam9x5()) {
  54. switch (extension_id) {
  55. case ARCH_EXID_AT91SAM9G15:
  56. return "AT91SAM9G15";
  57. case ARCH_EXID_AT91SAM9G25:
  58. return "AT91SAM9G25";
  59. case ARCH_EXID_AT91SAM9G35:
  60. return "AT91SAM9G35";
  61. case ARCH_EXID_AT91SAM9X25:
  62. return "AT91SAM9X25";
  63. case ARCH_EXID_AT91SAM9X35:
  64. return "AT91SAM9X35";
  65. default:
  66. return "Unknown CPU type";
  67. }
  68. } else {
  69. return "Unknown CPU type";
  70. }
  71. }
  72. void at91_seriald_hw_init(void)
  73. {
  74. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  75. at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
  76. at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
  77. writel(1 << ATMEL_ID_SYS, &pmc->pcer);
  78. }
  79. void at91_serial0_hw_init(void)
  80. {
  81. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  82. at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */
  83. at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */
  84. writel(1 << ATMEL_ID_USART0, &pmc->pcer);
  85. }
  86. void at91_serial1_hw_init(void)
  87. {
  88. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  89. at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */
  90. at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */
  91. writel(1 << ATMEL_ID_USART1, &pmc->pcer);
  92. }
  93. void at91_serial2_hw_init(void)
  94. {
  95. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  96. at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */
  97. at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */
  98. writel(1 << ATMEL_ID_USART2, &pmc->pcer);
  99. }
  100. void at91_mci_hw_init(void)
  101. {
  102. /* Initialize the MCI0 */
  103. at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */
  104. at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */
  105. at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */
  106. at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */
  107. at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */
  108. at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */
  109. /* Enable clock for MCI0 */
  110. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  111. writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
  112. }
  113. #ifdef CONFIG_ATMEL_SPI
  114. void at91_spi0_hw_init(unsigned long cs_mask)
  115. {
  116. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  117. at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
  118. at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
  119. at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
  120. /* Enable clock */
  121. writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
  122. if (cs_mask & (1 << 0))
  123. at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
  124. if (cs_mask & (1 << 1))
  125. at91_set_b_periph(AT91_PIO_PORTA, 7, 0);
  126. if (cs_mask & (1 << 2))
  127. at91_set_b_periph(AT91_PIO_PORTA, 1, 0);
  128. if (cs_mask & (1 << 3))
  129. at91_set_b_periph(AT91_PIO_PORTB, 3, 0);
  130. if (cs_mask & (1 << 4))
  131. at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
  132. if (cs_mask & (1 << 5))
  133. at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
  134. if (cs_mask & (1 << 6))
  135. at91_set_pio_output(AT91_PIO_PORTA, 1, 0);
  136. if (cs_mask & (1 << 7))
  137. at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
  138. }
  139. void at91_spi1_hw_init(unsigned long cs_mask)
  140. {
  141. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  142. at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
  143. at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
  144. at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
  145. /* Enable clock */
  146. writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
  147. if (cs_mask & (1 << 0))
  148. at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
  149. if (cs_mask & (1 << 1))
  150. at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
  151. if (cs_mask & (1 << 2))
  152. at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
  153. if (cs_mask & (1 << 3))
  154. at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
  155. if (cs_mask & (1 << 4))
  156. at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
  157. if (cs_mask & (1 << 5))
  158. at91_set_pio_output(AT91_PIO_PORTA, 0, 0);
  159. if (cs_mask & (1 << 6))
  160. at91_set_pio_output(AT91_PIO_PORTA, 31, 0);
  161. if (cs_mask & (1 << 7))
  162. at91_set_pio_output(AT91_PIO_PORTA, 30, 0);
  163. }
  164. #endif
  165. #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
  166. void at91_uhp_hw_init(void)
  167. {
  168. /* Enable VBus on UHP ports */
  169. at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */
  170. at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */
  171. #if defined(CONFIG_USB_OHCI_NEW)
  172. /* port C is OHCI only */
  173. at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */
  174. #endif
  175. }
  176. #endif
  177. #ifdef CONFIG_MACB
  178. void at91_macb_hw_init(void)
  179. {
  180. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  181. if (has_emac0()) {
  182. /* Enable EMAC0 clock */
  183. writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  184. /* EMAC0 pins setup */
  185. at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
  186. at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
  187. at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
  188. at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
  189. at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
  190. at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
  191. at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
  192. at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
  193. at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
  194. at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
  195. }
  196. if (has_emac1()) {
  197. /* Enable EMAC1 clock */
  198. writel(1 << ATMEL_ID_EMAC1, &pmc->pcer);
  199. /* EMAC1 pins setup */
  200. at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */
  201. at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */
  202. at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */
  203. at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */
  204. at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */
  205. at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */
  206. at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */
  207. at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */
  208. at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */
  209. at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */
  210. }
  211. #ifndef CONFIG_RMII
  212. /* Only emac0 support MII */
  213. if (has_emac0()) {
  214. at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
  215. at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
  216. at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
  217. at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
  218. at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
  219. at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
  220. at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
  221. at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
  222. }
  223. #endif
  224. }
  225. #endif