cpu.c 9.5 KB

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  1. /*
  2. * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. #include <common.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/flow.h>
  20. #include <asm/arch/pinmux.h>
  21. #include <asm/arch/tegra.h>
  22. #include <asm/arch-tegra/clk_rst.h>
  23. #include <asm/arch-tegra/pmc.h>
  24. #include "../tegra-common/cpu.h"
  25. /* Tegra114-specific CPU init code */
  26. static void enable_cpu_power_rail(void)
  27. {
  28. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  29. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  30. u32 reg;
  31. debug("enable_cpu_power_rail entry\n");
  32. /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
  33. pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
  34. pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
  35. /*
  36. * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
  37. * set it for 25ms (102MHz * .025)
  38. */
  39. reg = 0x26E8F0;
  40. writel(reg, &pmc->pmc_cpupwrgood_timer);
  41. /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
  42. clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
  43. setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
  44. /*
  45. * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
  46. * to 408 to satisfy the requirement of having at least 16 CPU clock
  47. * cycles before clamp removal.
  48. */
  49. clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
  50. setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
  51. }
  52. static void enable_cpu_clocks(void)
  53. {
  54. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  55. u32 reg;
  56. debug("enable_cpu_clocks entry\n");
  57. /* Wait for PLL-X to lock */
  58. do {
  59. reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
  60. } while ((reg & (1 << 27)) == 0);
  61. /* Wait until all clocks are stable */
  62. udelay(PLL_STABILIZATION_DELAY);
  63. writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
  64. writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
  65. /* Always enable the main CPU complex clocks */
  66. clock_enable(PERIPH_ID_CPU);
  67. clock_enable(PERIPH_ID_CPULP);
  68. clock_enable(PERIPH_ID_CPUG);
  69. }
  70. static void remove_cpu_resets(void)
  71. {
  72. struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  73. u32 reg;
  74. debug("remove_cpu_resets entry\n");
  75. /* Take the slow non-CPU partition out of reset */
  76. reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
  77. writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
  78. /* Take the fast non-CPU partition out of reset */
  79. reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
  80. writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
  81. /* Clear the SW-controlled reset of the slow cluster */
  82. reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
  83. reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
  84. writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
  85. /* Clear the SW-controlled reset of the fast cluster */
  86. reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
  87. reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
  88. reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
  89. reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
  90. reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
  91. writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
  92. }
  93. /**
  94. * The T114 requires some special clock initialization, including setting up
  95. * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
  96. */
  97. void t114_init_clocks(void)
  98. {
  99. struct clk_rst_ctlr *clkrst =
  100. (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  101. struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
  102. u32 val;
  103. debug("t114_init_clocks entry\n");
  104. /* Set active CPU cluster to G */
  105. clrbits_le32(&flow->cluster_control, 1);
  106. /*
  107. * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
  108. * at 108 MHz. This is glitch free as only the source is changed, no
  109. * special precaution needed.
  110. */
  111. val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
  112. (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
  113. (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
  114. (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
  115. (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
  116. writel(val, &clkrst->crc_sclk_brst_pol);
  117. writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
  118. debug("Setting up PLLX\n");
  119. init_pllx();
  120. val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
  121. writel(val, &clkrst->crc_clk_sys_rate);
  122. /* Enable clocks to required peripherals. TBD - minimize this list */
  123. debug("Enabling clocks\n");
  124. clock_set_enable(PERIPH_ID_CACHE2, 1);
  125. clock_set_enable(PERIPH_ID_GPIO, 1);
  126. clock_set_enable(PERIPH_ID_TMR, 1);
  127. clock_set_enable(PERIPH_ID_RTC, 1);
  128. clock_set_enable(PERIPH_ID_CPU, 1);
  129. clock_set_enable(PERIPH_ID_EMC, 1);
  130. clock_set_enable(PERIPH_ID_I2C5, 1);
  131. clock_set_enable(PERIPH_ID_FUSE, 1);
  132. clock_set_enable(PERIPH_ID_PMC, 1);
  133. clock_set_enable(PERIPH_ID_APBDMA, 1);
  134. clock_set_enable(PERIPH_ID_MEM, 1);
  135. clock_set_enable(PERIPH_ID_IRAMA, 1);
  136. clock_set_enable(PERIPH_ID_IRAMB, 1);
  137. clock_set_enable(PERIPH_ID_IRAMC, 1);
  138. clock_set_enable(PERIPH_ID_IRAMD, 1);
  139. clock_set_enable(PERIPH_ID_CORESIGHT, 1);
  140. clock_set_enable(PERIPH_ID_MSELECT, 1);
  141. clock_set_enable(PERIPH_ID_EMC1, 1);
  142. clock_set_enable(PERIPH_ID_MC1, 1);
  143. clock_set_enable(PERIPH_ID_DVFS, 1);
  144. /* Switch MSELECT clock to PLLP (00) */
  145. clock_ll_set_source(PERIPH_ID_MSELECT, 0);
  146. /*
  147. * Clock divider request for 102MHz would setup MSELECT clock as
  148. * 102MHz for PLLP base 408MHz
  149. */
  150. clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
  151. (NVBL_PLLP_KHZ/102000));
  152. /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
  153. clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
  154. /* Give clocks time to stabilize */
  155. udelay(1000);
  156. /* Take required peripherals out of reset */
  157. debug("Taking periphs out of reset\n");
  158. reset_set_enable(PERIPH_ID_CACHE2, 0);
  159. reset_set_enable(PERIPH_ID_GPIO, 0);
  160. reset_set_enable(PERIPH_ID_TMR, 0);
  161. reset_set_enable(PERIPH_ID_COP, 0);
  162. reset_set_enable(PERIPH_ID_EMC, 0);
  163. reset_set_enable(PERIPH_ID_I2C5, 0);
  164. reset_set_enable(PERIPH_ID_FUSE, 0);
  165. reset_set_enable(PERIPH_ID_APBDMA, 0);
  166. reset_set_enable(PERIPH_ID_MEM, 0);
  167. reset_set_enable(PERIPH_ID_CORESIGHT, 0);
  168. reset_set_enable(PERIPH_ID_MSELECT, 0);
  169. reset_set_enable(PERIPH_ID_EMC1, 0);
  170. reset_set_enable(PERIPH_ID_MC1, 0);
  171. reset_set_enable(PERIPH_ID_DVFS, 0);
  172. debug("t114_init_clocks exit\n");
  173. }
  174. static int is_partition_powered(u32 mask)
  175. {
  176. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  177. u32 reg;
  178. /* Get power gate status */
  179. reg = readl(&pmc->pmc_pwrgate_status);
  180. return (reg & mask) == mask;
  181. }
  182. static int is_clamp_enabled(u32 mask)
  183. {
  184. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  185. u32 reg;
  186. /* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
  187. reg = readl(&pmc->pmc_pwrgate_timer_on);
  188. return (reg & mask) == mask;
  189. }
  190. static void power_partition(u32 status, u32 partid)
  191. {
  192. struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
  193. debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid);
  194. /* Is the partition already on? */
  195. if (!is_partition_powered(status)) {
  196. /* No, toggle the partition power state (OFF -> ON) */
  197. debug("power_partition, toggling state\n");
  198. clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
  199. setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
  200. setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
  201. /* Wait for the power to come up */
  202. while (!is_partition_powered(status))
  203. ;
  204. /* Wait for the clamp status to be cleared */
  205. while (is_clamp_enabled(status))
  206. ;
  207. /* Give I/O signals time to stabilize */
  208. udelay(IO_STABILIZATION_DELAY);
  209. }
  210. }
  211. void powerup_cpus(void)
  212. {
  213. debug("powerup_cpus entry\n");
  214. /* We boot to the fast cluster */
  215. debug("powerup_cpus entry: G cluster\n");
  216. /* Power up the fast cluster rail partition */
  217. power_partition(CRAIL, CRAILID);
  218. /* Power up the fast cluster non-CPU partition */
  219. power_partition(C0NC, C0NCID);
  220. /* Power up the fast cluster CPU0 partition */
  221. power_partition(CE0, CE0ID);
  222. }
  223. void start_cpu(u32 reset_vector)
  224. {
  225. u32 imme, inst;
  226. debug("start_cpu entry, reset_vector = %x\n", reset_vector);
  227. t114_init_clocks();
  228. /* Enable VDD_CPU */
  229. enable_cpu_power_rail();
  230. /* Get the CPU(s) running */
  231. enable_cpu_clocks();
  232. /* Enable CoreSight */
  233. clock_enable_coresight(1);
  234. /* Take CPU(s) out of reset */
  235. remove_cpu_resets();
  236. /* Set the entry point for CPU execution from reset */
  237. /*
  238. * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
  239. * See nvbug 1193357 for details.
  240. */
  241. /* mov r0, #lsb(reset_vector) */
  242. imme = reset_vector & 0xffff;
  243. inst = imme & 0xfff;
  244. inst |= ((imme >> 12) << 16);
  245. inst |= 0xe3000000;
  246. writel(inst, 0x4003fff0);
  247. /* movt r0, #msb(reset_vector) */
  248. imme = (reset_vector >> 16) & 0xffff;
  249. inst = imme & 0xfff;
  250. inst |= ((imme >> 12) << 16);
  251. inst |= 0xe3400000;
  252. writel(inst, 0x4003fff4);
  253. /* bx r0 */
  254. writel(0xe12fff10, 0x4003fff8);
  255. /* b -12 */
  256. imme = (u32)-20;
  257. inst = (imme >> 2) & 0xffffff;
  258. inst |= 0xea000000;
  259. writel(inst, 0x4003fffc);
  260. /* Write to orignal location for compatibility */
  261. writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
  262. /* If the CPU(s) don't already have power, power 'em up */
  263. powerup_cpus();
  264. }