generic.c 13 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Sascha Hauer, Pengutronix
  4. *
  5. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <common.h>
  26. #include <div64.h>
  27. #include <asm/io.h>
  28. #include <asm/errno.h>
  29. #include <asm/arch/imx-regs.h>
  30. #include <asm/arch/crm_regs.h>
  31. #include <asm/arch/clock.h>
  32. #include <asm/arch/sys_proto.h>
  33. #ifdef CONFIG_FSL_ESDHC
  34. #include <fsl_esdhc.h>
  35. #endif
  36. #include <netdev.h>
  37. #include <spl.h>
  38. #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
  39. #define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
  40. #define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
  41. #define CLK_CODE_PATH(c) ((c) & 0xFF)
  42. #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
  43. #ifdef CONFIG_FSL_ESDHC
  44. DECLARE_GLOBAL_DATA_PTR;
  45. #endif
  46. static int g_clk_mux_auto[8] = {
  47. CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
  48. CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
  49. };
  50. static int g_clk_mux_consumer[16] = {
  51. CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
  52. -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
  53. CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
  54. -1, -1, CLK_CODE(4, 2, 0), -1,
  55. };
  56. static int hsp_div_table[3][16] = {
  57. {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
  58. {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
  59. {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
  60. };
  61. u32 get_cpu_rev(void)
  62. {
  63. int reg;
  64. struct iim_regs *iim =
  65. (struct iim_regs *)IIM_BASE_ADDR;
  66. reg = readl(&iim->iim_srev);
  67. if (!reg) {
  68. reg = readw(ROMPATCH_REV);
  69. reg <<= 4;
  70. } else {
  71. reg += CHIP_REV_1_0;
  72. }
  73. return 0x35000 + (reg & 0xFF);
  74. }
  75. static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
  76. {
  77. int *pclk_mux;
  78. if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  79. pclk_mux = g_clk_mux_consumer +
  80. ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  81. MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  82. } else {
  83. pclk_mux = g_clk_mux_auto +
  84. ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
  85. MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
  86. }
  87. if ((*pclk_mux) == -1)
  88. return -1;
  89. if (fi && fd) {
  90. if (!CLK_CODE_PATH(*pclk_mux)) {
  91. *fi = *fd = 1;
  92. return CLK_CODE_ARM(*pclk_mux);
  93. }
  94. if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  95. *fi = 3;
  96. *fd = 4;
  97. } else {
  98. *fi = 2;
  99. *fd = 3;
  100. }
  101. }
  102. return CLK_CODE_ARM(*pclk_mux);
  103. }
  104. static int get_ahb_div(u32 pdr0)
  105. {
  106. int *pclk_mux;
  107. pclk_mux = g_clk_mux_consumer +
  108. ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  109. MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  110. if ((*pclk_mux) == -1)
  111. return -1;
  112. return CLK_CODE_AHB(*pclk_mux);
  113. }
  114. static u32 decode_pll(u32 reg, u32 infreq)
  115. {
  116. u32 mfi = (reg >> 10) & 0xf;
  117. s32 mfn = reg & 0x3ff;
  118. u32 mfd = (reg >> 16) & 0x3ff;
  119. u32 pd = (reg >> 26) & 0xf;
  120. mfi = mfi <= 5 ? 5 : mfi;
  121. mfn = mfn >= 512 ? mfn - 1024 : mfn;
  122. mfd += 1;
  123. pd += 1;
  124. return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
  125. mfd * pd);
  126. }
  127. static u32 get_mcu_main_clk(void)
  128. {
  129. u32 arm_div = 0, fi = 0, fd = 0;
  130. struct ccm_regs *ccm =
  131. (struct ccm_regs *)IMX_CCM_BASE;
  132. arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
  133. fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
  134. return fi / (arm_div * fd);
  135. }
  136. static u32 get_ipg_clk(void)
  137. {
  138. u32 freq = get_mcu_main_clk();
  139. struct ccm_regs *ccm =
  140. (struct ccm_regs *)IMX_CCM_BASE;
  141. u32 pdr0 = readl(&ccm->pdr0);
  142. return freq / (get_ahb_div(pdr0) * 2);
  143. }
  144. static u32 get_ipg_per_clk(void)
  145. {
  146. u32 freq = get_mcu_main_clk();
  147. struct ccm_regs *ccm =
  148. (struct ccm_regs *)IMX_CCM_BASE;
  149. u32 pdr0 = readl(&ccm->pdr0);
  150. u32 pdr4 = readl(&ccm->pdr4);
  151. u32 div;
  152. if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
  153. div = CCM_GET_DIVIDER(pdr4,
  154. MXC_CCM_PDR4_PER0_PODF_MASK,
  155. MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
  156. } else {
  157. div = CCM_GET_DIVIDER(pdr0,
  158. MXC_CCM_PDR0_PER_PODF_MASK,
  159. MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
  160. div *= get_ahb_div(pdr0);
  161. }
  162. return freq / div;
  163. }
  164. u32 imx_get_uartclk(void)
  165. {
  166. u32 freq;
  167. struct ccm_regs *ccm =
  168. (struct ccm_regs *)IMX_CCM_BASE;
  169. u32 pdr4 = readl(&ccm->pdr4);
  170. if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
  171. freq = get_mcu_main_clk();
  172. else
  173. freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  174. freq /= CCM_GET_DIVIDER(pdr4,
  175. MXC_CCM_PDR4_UART_PODF_MASK,
  176. MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
  177. return freq;
  178. }
  179. unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
  180. {
  181. u32 nfc_pdf, hsp_podf;
  182. u32 pll, ret_val = 0, usb_podf;
  183. struct ccm_regs *ccm =
  184. (struct ccm_regs *)IMX_CCM_BASE;
  185. u32 reg = readl(&ccm->pdr0);
  186. u32 reg4 = readl(&ccm->pdr4);
  187. reg |= 0x1;
  188. switch (clk) {
  189. case CPU_CLK:
  190. ret_val = get_mcu_main_clk();
  191. break;
  192. case AHB_CLK:
  193. ret_val = get_mcu_main_clk();
  194. break;
  195. case HSP_CLK:
  196. if (reg & CLKMODE_CONSUMER) {
  197. hsp_podf = (reg >> 20) & 0x3;
  198. pll = get_mcu_main_clk();
  199. hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
  200. if (hsp_podf > 0) {
  201. ret_val = pll / hsp_podf;
  202. } else {
  203. puts("mismatch HSP with ARM clock setting\n");
  204. ret_val = 0;
  205. }
  206. } else {
  207. ret_val = get_mcu_main_clk();
  208. }
  209. break;
  210. case IPG_CLK:
  211. ret_val = get_ipg_clk();
  212. break;
  213. case IPG_PER_CLK:
  214. ret_val = get_ipg_per_clk();
  215. break;
  216. case NFC_CLK:
  217. nfc_pdf = (reg4 >> 28) & 0xF;
  218. pll = get_mcu_main_clk();
  219. /* AHB/nfc_pdf */
  220. ret_val = pll / (nfc_pdf + 1);
  221. break;
  222. case USB_CLK:
  223. usb_podf = (reg4 >> 22) & 0x3F;
  224. if (reg4 & 0x200)
  225. pll = get_mcu_main_clk();
  226. else
  227. pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  228. ret_val = pll / (usb_podf + 1);
  229. break;
  230. default:
  231. printf("Unknown clock: %d\n", clk);
  232. break;
  233. }
  234. return ret_val;
  235. }
  236. unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
  237. {
  238. u32 ret_val = 0, pdf, pre_pdf, clk_sel;
  239. struct ccm_regs *ccm =
  240. (struct ccm_regs *)IMX_CCM_BASE;
  241. u32 mpdr2 = readl(&ccm->pdr2);
  242. u32 mpdr3 = readl(&ccm->pdr3);
  243. u32 mpdr4 = readl(&ccm->pdr4);
  244. switch (clk) {
  245. case UART1_BAUD:
  246. case UART2_BAUD:
  247. case UART3_BAUD:
  248. clk_sel = mpdr3 & (1 << 14);
  249. pdf = (mpdr4 >> 10) & 0x3F;
  250. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  251. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  252. break;
  253. case SSI1_BAUD:
  254. pre_pdf = (mpdr2 >> 24) & 0x7;
  255. pdf = mpdr2 & 0x3F;
  256. clk_sel = mpdr2 & (1 << 6);
  257. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  258. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  259. ((pre_pdf + 1) * (pdf + 1));
  260. break;
  261. case SSI2_BAUD:
  262. pre_pdf = (mpdr2 >> 27) & 0x7;
  263. pdf = (mpdr2 >> 8) & 0x3F;
  264. clk_sel = mpdr2 & (1 << 6);
  265. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  266. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  267. ((pre_pdf + 1) * (pdf + 1));
  268. break;
  269. case CSI_BAUD:
  270. clk_sel = mpdr2 & (1 << 7);
  271. pdf = (mpdr2 >> 16) & 0x3F;
  272. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  273. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  274. break;
  275. case MSHC_CLK:
  276. pre_pdf = readl(&ccm->pdr1);
  277. clk_sel = (pre_pdf & 0x80);
  278. pdf = (pre_pdf >> 22) & 0x3F;
  279. pre_pdf = (pre_pdf >> 28) & 0x7;
  280. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  281. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  282. ((pre_pdf + 1) * (pdf + 1));
  283. break;
  284. case ESDHC1_CLK:
  285. clk_sel = mpdr3 & 0x40;
  286. pdf = mpdr3 & 0x3F;
  287. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  288. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  289. break;
  290. case ESDHC2_CLK:
  291. clk_sel = mpdr3 & 0x40;
  292. pdf = (mpdr3 >> 8) & 0x3F;
  293. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  294. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  295. break;
  296. case ESDHC3_CLK:
  297. clk_sel = mpdr3 & 0x40;
  298. pdf = (mpdr3 >> 16) & 0x3F;
  299. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  300. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  301. break;
  302. case SPDIF_CLK:
  303. clk_sel = mpdr3 & 0x400000;
  304. pre_pdf = (mpdr3 >> 29) & 0x7;
  305. pdf = (mpdr3 >> 23) & 0x3F;
  306. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  307. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  308. ((pre_pdf + 1) * (pdf + 1));
  309. break;
  310. default:
  311. printf("%s(): This clock: %d not supported yet\n",
  312. __func__, clk);
  313. break;
  314. }
  315. return ret_val;
  316. }
  317. unsigned int mxc_get_clock(enum mxc_clock clk)
  318. {
  319. switch (clk) {
  320. case MXC_ARM_CLK:
  321. return get_mcu_main_clk();
  322. case MXC_AHB_CLK:
  323. break;
  324. case MXC_IPG_CLK:
  325. return get_ipg_clk();
  326. case MXC_IPG_PERCLK:
  327. case MXC_I2C_CLK:
  328. return get_ipg_per_clk();
  329. case MXC_UART_CLK:
  330. return imx_get_uartclk();
  331. case MXC_ESDHC1_CLK:
  332. return mxc_get_peri_clock(ESDHC1_CLK);
  333. case MXC_ESDHC2_CLK:
  334. return mxc_get_peri_clock(ESDHC2_CLK);
  335. case MXC_ESDHC3_CLK:
  336. return mxc_get_peri_clock(ESDHC3_CLK);
  337. case MXC_USB_CLK:
  338. return mxc_get_main_clock(USB_CLK);
  339. case MXC_FEC_CLK:
  340. return get_ipg_clk();
  341. case MXC_CSPI_CLK:
  342. return get_ipg_clk();
  343. }
  344. return -1;
  345. }
  346. #ifdef CONFIG_FEC_MXC
  347. /*
  348. * The MX35 has no fuse for MAC, return a NULL MAC
  349. */
  350. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  351. {
  352. memset(mac, 0, 6);
  353. }
  354. u32 imx_get_fecclk(void)
  355. {
  356. return mxc_get_clock(MXC_IPG_CLK);
  357. }
  358. #endif
  359. int do_mx35_showclocks(cmd_tbl_t *cmdtp,
  360. int flag, int argc, char * const argv[])
  361. {
  362. u32 cpufreq = get_mcu_main_clk();
  363. printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
  364. printf("ipg clock : %dHz\n", get_ipg_clk());
  365. printf("ipg per clock : %dHz\n", get_ipg_per_clk());
  366. printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
  367. return 0;
  368. }
  369. U_BOOT_CMD(
  370. clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
  371. "display clocks",
  372. ""
  373. );
  374. #if defined(CONFIG_DISPLAY_CPUINFO)
  375. static char *get_reset_cause(void)
  376. {
  377. /* read RCSR register from CCM module */
  378. struct ccm_regs *ccm =
  379. (struct ccm_regs *)IMX_CCM_BASE;
  380. u32 cause = readl(&ccm->rcsr) & 0x0F;
  381. switch (cause) {
  382. case 0x0000:
  383. return "POR";
  384. case 0x0002:
  385. return "JTAG";
  386. case 0x0004:
  387. return "RST";
  388. case 0x0008:
  389. return "WDOG";
  390. default:
  391. return "unknown reset";
  392. }
  393. }
  394. int print_cpuinfo(void)
  395. {
  396. u32 srev = get_cpu_rev();
  397. printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
  398. (srev & 0xF0) >> 4, (srev & 0x0F),
  399. get_mcu_main_clk() / 1000000);
  400. printf("Reset cause: %s\n", get_reset_cause());
  401. return 0;
  402. }
  403. #endif
  404. /*
  405. * Initializes on-chip ethernet controllers.
  406. * to override, implement board_eth_init()
  407. */
  408. int cpu_eth_init(bd_t *bis)
  409. {
  410. int rc = -ENODEV;
  411. #if defined(CONFIG_FEC_MXC)
  412. rc = fecmxc_initialize(bis);
  413. #endif
  414. return rc;
  415. }
  416. #ifdef CONFIG_FSL_ESDHC
  417. /*
  418. * Initializes on-chip MMC controllers.
  419. * to override, implement board_mmc_init()
  420. */
  421. int cpu_mmc_init(bd_t *bis)
  422. {
  423. return fsl_esdhc_mmc_init(bis);
  424. }
  425. #endif
  426. int get_clocks(void)
  427. {
  428. #ifdef CONFIG_FSL_ESDHC
  429. #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
  430. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  431. #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
  432. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  433. #else
  434. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  435. #endif
  436. #endif
  437. return 0;
  438. }
  439. #define RCSR_MEM_CTL_WEIM 0
  440. #define RCSR_MEM_CTL_NAND 1
  441. #define RCSR_MEM_CTL_ATA 2
  442. #define RCSR_MEM_CTL_EXPANSION 3
  443. #define RCSR_MEM_TYPE_NOR 0
  444. #define RCSR_MEM_TYPE_ONENAND 2
  445. #define RCSR_MEM_TYPE_SD 0
  446. #define RCSR_MEM_TYPE_I2C 2
  447. #define RCSR_MEM_TYPE_SPI 3
  448. u32 spl_boot_device(void)
  449. {
  450. struct ccm_regs *ccm =
  451. (struct ccm_regs *)IMX_CCM_BASE;
  452. u32 rcsr = readl(&ccm->rcsr);
  453. u32 mem_type, mem_ctl;
  454. /* In external mode, no boot device is returned */
  455. if ((rcsr >> 10) & 0x03)
  456. return BOOT_DEVICE_NONE;
  457. mem_ctl = (rcsr >> 25) & 0x03;
  458. mem_type = (rcsr >> 23) & 0x03;
  459. switch (mem_ctl) {
  460. case RCSR_MEM_CTL_WEIM:
  461. switch (mem_type) {
  462. case RCSR_MEM_TYPE_NOR:
  463. return BOOT_DEVICE_NOR;
  464. case RCSR_MEM_TYPE_ONENAND:
  465. return BOOT_DEVICE_ONENAND;
  466. default:
  467. return BOOT_DEVICE_NONE;
  468. }
  469. case RCSR_MEM_CTL_NAND:
  470. return BOOT_DEVICE_NAND;
  471. case RCSR_MEM_CTL_EXPANSION:
  472. switch (mem_type) {
  473. case RCSR_MEM_TYPE_SD:
  474. return BOOT_DEVICE_MMC1;
  475. case RCSR_MEM_TYPE_I2C:
  476. return BOOT_DEVICE_I2C;
  477. case RCSR_MEM_TYPE_SPI:
  478. return BOOT_DEVICE_SPI;
  479. default:
  480. return BOOT_DEVICE_NONE;
  481. }
  482. }
  483. return BOOT_DEVICE_NONE;
  484. }
  485. #ifdef CONFIG_SPL_BUILD
  486. u32 spl_boot_mode(void)
  487. {
  488. switch (spl_boot_device()) {
  489. case BOOT_DEVICE_MMC1:
  490. #ifdef CONFIG_SPL_FAT_SUPPORT
  491. return MMCSD_MODE_FAT;
  492. #else
  493. return MMCSD_MODE_RAW;
  494. #endif
  495. break;
  496. case BOOT_DEVICE_NAND:
  497. return 0;
  498. break;
  499. default:
  500. puts("spl: ERROR: unsupported device\n");
  501. hang();
  502. }
  503. }
  504. #endif