fsl_esdhc.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
  4. * Copyright 2019 NXP Semiconductors
  5. * Andy Fleming
  6. *
  7. * Based vaguely on the pxa mmc code:
  8. * (C) Copyright 2003
  9. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  10. */
  11. #include <config.h>
  12. #include <common.h>
  13. #include <command.h>
  14. #include <clk.h>
  15. #include <errno.h>
  16. #include <hwconfig.h>
  17. #include <mmc.h>
  18. #include <part.h>
  19. #include <malloc.h>
  20. #include <fsl_esdhc.h>
  21. #include <fdt_support.h>
  22. #include <asm/io.h>
  23. #include <dm.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. struct fsl_esdhc {
  26. uint dsaddr; /* SDMA system address register */
  27. uint blkattr; /* Block attributes register */
  28. uint cmdarg; /* Command argument register */
  29. uint xfertyp; /* Transfer type register */
  30. uint cmdrsp0; /* Command response 0 register */
  31. uint cmdrsp1; /* Command response 1 register */
  32. uint cmdrsp2; /* Command response 2 register */
  33. uint cmdrsp3; /* Command response 3 register */
  34. uint datport; /* Buffer data port register */
  35. uint prsstat; /* Present state register */
  36. uint proctl; /* Protocol control register */
  37. uint sysctl; /* System Control Register */
  38. uint irqstat; /* Interrupt status register */
  39. uint irqstaten; /* Interrupt status enable register */
  40. uint irqsigen; /* Interrupt signal enable register */
  41. uint autoc12err; /* Auto CMD error status register */
  42. uint hostcapblt; /* Host controller capabilities register */
  43. uint wml; /* Watermark level register */
  44. char reserved1[8]; /* reserved */
  45. uint fevt; /* Force event register */
  46. uint admaes; /* ADMA error status register */
  47. uint adsaddr; /* ADMA system address register */
  48. char reserved2[160];
  49. uint hostver; /* Host controller version register */
  50. char reserved3[4]; /* reserved */
  51. uint dmaerraddr; /* DMA error address register */
  52. char reserved4[4]; /* reserved */
  53. uint dmaerrattr; /* DMA error attribute register */
  54. char reserved5[4]; /* reserved */
  55. uint hostcapblt2; /* Host controller capabilities register 2 */
  56. char reserved6[756]; /* reserved */
  57. uint esdhcctl; /* eSDHC control register */
  58. };
  59. struct fsl_esdhc_plat {
  60. struct mmc_config cfg;
  61. struct mmc mmc;
  62. };
  63. /**
  64. * struct fsl_esdhc_priv
  65. *
  66. * @esdhc_regs: registers of the sdhc controller
  67. * @sdhc_clk: Current clk of the sdhc controller
  68. * @bus_width: bus width, 1bit, 4bit or 8bit
  69. * @cfg: mmc config
  70. * @mmc: mmc
  71. * Following is used when Driver Model is enabled for MMC
  72. * @dev: pointer for the device
  73. * @cd_gpio: gpio for card detection
  74. * @wp_gpio: gpio for write protection
  75. */
  76. struct fsl_esdhc_priv {
  77. struct fsl_esdhc *esdhc_regs;
  78. unsigned int sdhc_clk;
  79. struct clk per_clk;
  80. unsigned int clock;
  81. #if !CONFIG_IS_ENABLED(DM_MMC)
  82. struct mmc *mmc;
  83. #endif
  84. struct udevice *dev;
  85. };
  86. /* Return the XFERTYP flags for a given command and data packet */
  87. static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  88. {
  89. uint xfertyp = 0;
  90. if (data) {
  91. xfertyp |= XFERTYP_DPSEL;
  92. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  93. xfertyp |= XFERTYP_DMAEN;
  94. #endif
  95. if (data->blocks > 1) {
  96. xfertyp |= XFERTYP_MSBSEL;
  97. xfertyp |= XFERTYP_BCEN;
  98. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  99. xfertyp |= XFERTYP_AC12EN;
  100. #endif
  101. }
  102. if (data->flags & MMC_DATA_READ)
  103. xfertyp |= XFERTYP_DTDSEL;
  104. }
  105. if (cmd->resp_type & MMC_RSP_CRC)
  106. xfertyp |= XFERTYP_CCCEN;
  107. if (cmd->resp_type & MMC_RSP_OPCODE)
  108. xfertyp |= XFERTYP_CICEN;
  109. if (cmd->resp_type & MMC_RSP_136)
  110. xfertyp |= XFERTYP_RSPTYP_136;
  111. else if (cmd->resp_type & MMC_RSP_BUSY)
  112. xfertyp |= XFERTYP_RSPTYP_48_BUSY;
  113. else if (cmd->resp_type & MMC_RSP_PRESENT)
  114. xfertyp |= XFERTYP_RSPTYP_48;
  115. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  116. xfertyp |= XFERTYP_CMDTYP_ABORT;
  117. return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
  118. }
  119. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  120. /*
  121. * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
  122. */
  123. static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
  124. struct mmc_data *data)
  125. {
  126. struct fsl_esdhc *regs = priv->esdhc_regs;
  127. uint blocks;
  128. char *buffer;
  129. uint databuf;
  130. uint size;
  131. uint irqstat;
  132. ulong start;
  133. if (data->flags & MMC_DATA_READ) {
  134. blocks = data->blocks;
  135. buffer = data->dest;
  136. while (blocks) {
  137. start = get_timer(0);
  138. size = data->blocksize;
  139. irqstat = esdhc_read32(&regs->irqstat);
  140. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
  141. if (get_timer(start) > PIO_TIMEOUT) {
  142. printf("\nData Read Failed in PIO Mode.");
  143. return;
  144. }
  145. }
  146. while (size && (!(irqstat & IRQSTAT_TC))) {
  147. udelay(100); /* Wait before last byte transfer complete */
  148. irqstat = esdhc_read32(&regs->irqstat);
  149. databuf = in_le32(&regs->datport);
  150. *((uint *)buffer) = databuf;
  151. buffer += 4;
  152. size -= 4;
  153. }
  154. blocks--;
  155. }
  156. } else {
  157. blocks = data->blocks;
  158. buffer = (char *)data->src;
  159. while (blocks) {
  160. start = get_timer(0);
  161. size = data->blocksize;
  162. irqstat = esdhc_read32(&regs->irqstat);
  163. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
  164. if (get_timer(start) > PIO_TIMEOUT) {
  165. printf("\nData Write Failed in PIO Mode.");
  166. return;
  167. }
  168. }
  169. while (size && (!(irqstat & IRQSTAT_TC))) {
  170. udelay(100); /* Wait before last byte transfer complete */
  171. databuf = *((uint *)buffer);
  172. buffer += 4;
  173. size -= 4;
  174. irqstat = esdhc_read32(&regs->irqstat);
  175. out_le32(&regs->datport, databuf);
  176. }
  177. blocks--;
  178. }
  179. }
  180. }
  181. #endif
  182. static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  183. struct mmc_data *data)
  184. {
  185. int timeout;
  186. struct fsl_esdhc *regs = priv->esdhc_regs;
  187. #if defined(CONFIG_FSL_LAYERSCAPE)
  188. dma_addr_t addr;
  189. #endif
  190. uint wml_value;
  191. wml_value = data->blocksize/4;
  192. if (data->flags & MMC_DATA_READ) {
  193. if (wml_value > WML_RD_WML_MAX)
  194. wml_value = WML_RD_WML_MAX_VAL;
  195. esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
  196. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  197. #if defined(CONFIG_FSL_LAYERSCAPE)
  198. addr = virt_to_phys((void *)(data->dest));
  199. if (upper_32_bits(addr))
  200. printf("Error found for upper 32 bits\n");
  201. else
  202. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  203. #else
  204. esdhc_write32(&regs->dsaddr, (u32)data->dest);
  205. #endif
  206. #endif
  207. } else {
  208. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  209. flush_dcache_range((ulong)data->src,
  210. (ulong)data->src+data->blocks
  211. *data->blocksize);
  212. #endif
  213. if (wml_value > WML_WR_WML_MAX)
  214. wml_value = WML_WR_WML_MAX_VAL;
  215. if (!(esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL)) {
  216. printf("Can not write to locked SD card.\n");
  217. return -EINVAL;
  218. }
  219. esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
  220. wml_value << 16);
  221. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  222. #if defined(CONFIG_FSL_LAYERSCAPE)
  223. addr = virt_to_phys((void *)(data->src));
  224. if (upper_32_bits(addr))
  225. printf("Error found for upper 32 bits\n");
  226. else
  227. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  228. #else
  229. esdhc_write32(&regs->dsaddr, (u32)data->src);
  230. #endif
  231. #endif
  232. }
  233. esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
  234. /* Calculate the timeout period for data transactions */
  235. /*
  236. * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
  237. * 2)Timeout period should be minimum 0.250sec as per SD Card spec
  238. * So, Number of SD Clock cycles for 0.25sec should be minimum
  239. * (SD Clock/sec * 0.25 sec) SD Clock cycles
  240. * = (mmc->clock * 1/4) SD Clock cycles
  241. * As 1) >= 2)
  242. * => (2^(timeout+13)) >= mmc->clock * 1/4
  243. * Taking log2 both the sides
  244. * => timeout + 13 >= log2(mmc->clock/4)
  245. * Rounding up to next power of 2
  246. * => timeout + 13 = log2(mmc->clock/4) + 1
  247. * => timeout + 13 = fls(mmc->clock/4)
  248. *
  249. * However, the MMC spec "It is strongly recommended for hosts to
  250. * implement more than 500ms timeout value even if the card
  251. * indicates the 250ms maximum busy length." Even the previous
  252. * value of 300ms is known to be insufficient for some cards.
  253. * So, we use
  254. * => timeout + 13 = fls(mmc->clock/2)
  255. */
  256. timeout = fls(mmc->clock/2);
  257. timeout -= 13;
  258. if (timeout > 14)
  259. timeout = 14;
  260. if (timeout < 0)
  261. timeout = 0;
  262. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  263. if ((timeout == 4) || (timeout == 8) || (timeout == 12))
  264. timeout++;
  265. #endif
  266. #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  267. timeout = 0xE;
  268. #endif
  269. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
  270. return 0;
  271. }
  272. static void check_and_invalidate_dcache_range
  273. (struct mmc_cmd *cmd,
  274. struct mmc_data *data) {
  275. unsigned start = 0;
  276. unsigned end = 0;
  277. unsigned size = roundup(ARCH_DMA_MINALIGN,
  278. data->blocks*data->blocksize);
  279. #if defined(CONFIG_FSL_LAYERSCAPE)
  280. dma_addr_t addr;
  281. addr = virt_to_phys((void *)(data->dest));
  282. if (upper_32_bits(addr))
  283. printf("Error found for upper 32 bits\n");
  284. else
  285. start = lower_32_bits(addr);
  286. #else
  287. start = (unsigned)data->dest;
  288. #endif
  289. end = start + size;
  290. invalidate_dcache_range(start, end);
  291. }
  292. /*
  293. * Sends a command out on the bus. Takes the mmc pointer,
  294. * a command pointer, and an optional data pointer.
  295. */
  296. static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  297. struct mmc_cmd *cmd, struct mmc_data *data)
  298. {
  299. int err = 0;
  300. uint xfertyp;
  301. uint irqstat;
  302. u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
  303. struct fsl_esdhc *regs = priv->esdhc_regs;
  304. unsigned long start;
  305. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  306. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  307. return 0;
  308. #endif
  309. esdhc_write32(&regs->irqstat, -1);
  310. sync();
  311. /* Wait for the bus to be idle */
  312. while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
  313. (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
  314. ;
  315. while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
  316. ;
  317. /* Wait at least 8 SD clock cycles before the next command */
  318. /*
  319. * Note: This is way more than 8 cycles, but 1ms seems to
  320. * resolve timing issues with some cards
  321. */
  322. udelay(1000);
  323. /* Set up for a data transfer if we have one */
  324. if (data) {
  325. err = esdhc_setup_data(priv, mmc, data);
  326. if(err)
  327. return err;
  328. if (data->flags & MMC_DATA_READ)
  329. check_and_invalidate_dcache_range(cmd, data);
  330. }
  331. /* Figure out the transfer arguments */
  332. xfertyp = esdhc_xfertyp(cmd, data);
  333. /* Mask all irqs */
  334. esdhc_write32(&regs->irqsigen, 0);
  335. /* Send the command */
  336. esdhc_write32(&regs->cmdarg, cmd->cmdarg);
  337. esdhc_write32(&regs->xfertyp, xfertyp);
  338. /* Wait for the command to complete */
  339. start = get_timer(0);
  340. while (!(esdhc_read32(&regs->irqstat) & flags)) {
  341. if (get_timer(start) > 1000) {
  342. err = -ETIMEDOUT;
  343. goto out;
  344. }
  345. }
  346. irqstat = esdhc_read32(&regs->irqstat);
  347. if (irqstat & CMD_ERR) {
  348. err = -ECOMM;
  349. goto out;
  350. }
  351. if (irqstat & IRQSTAT_CTOE) {
  352. err = -ETIMEDOUT;
  353. goto out;
  354. }
  355. /* Workaround for ESDHC errata ENGcm03648 */
  356. if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
  357. int timeout = 6000;
  358. /* Poll on DATA0 line for cmd with busy signal for 600 ms */
  359. while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
  360. PRSSTAT_DAT0)) {
  361. udelay(100);
  362. timeout--;
  363. }
  364. if (timeout <= 0) {
  365. printf("Timeout waiting for DAT0 to go high!\n");
  366. err = -ETIMEDOUT;
  367. goto out;
  368. }
  369. }
  370. /* Copy the response to the response buffer */
  371. if (cmd->resp_type & MMC_RSP_136) {
  372. u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
  373. cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
  374. cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
  375. cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
  376. cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
  377. cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
  378. cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
  379. cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
  380. cmd->response[3] = (cmdrsp0 << 8);
  381. } else
  382. cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
  383. /* Wait until all of the blocks are transferred */
  384. if (data) {
  385. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  386. esdhc_pio_read_write(priv, data);
  387. #else
  388. do {
  389. irqstat = esdhc_read32(&regs->irqstat);
  390. if (irqstat & IRQSTAT_DTOE) {
  391. err = -ETIMEDOUT;
  392. goto out;
  393. }
  394. if (irqstat & DATA_ERR) {
  395. err = -ECOMM;
  396. goto out;
  397. }
  398. } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
  399. /*
  400. * Need invalidate the dcache here again to avoid any
  401. * cache-fill during the DMA operations such as the
  402. * speculative pre-fetching etc.
  403. */
  404. if (data->flags & MMC_DATA_READ) {
  405. check_and_invalidate_dcache_range(cmd, data);
  406. }
  407. #endif
  408. }
  409. out:
  410. /* Reset CMD and DATA portions on error */
  411. if (err) {
  412. esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
  413. SYSCTL_RSTC);
  414. while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
  415. ;
  416. if (data) {
  417. esdhc_write32(&regs->sysctl,
  418. esdhc_read32(&regs->sysctl) |
  419. SYSCTL_RSTD);
  420. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
  421. ;
  422. }
  423. }
  424. esdhc_write32(&regs->irqstat, -1);
  425. return err;
  426. }
  427. static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
  428. {
  429. struct fsl_esdhc *regs = priv->esdhc_regs;
  430. int div = 1;
  431. int pre_div = 2;
  432. unsigned int sdhc_clk = priv->sdhc_clk;
  433. u32 time_out;
  434. u32 value;
  435. uint clk;
  436. if (clock < mmc->cfg->f_min)
  437. clock = mmc->cfg->f_min;
  438. while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
  439. pre_div *= 2;
  440. while (sdhc_clk / (div * pre_div) > clock && div < 16)
  441. div++;
  442. pre_div >>= 1;
  443. div -= 1;
  444. clk = (pre_div << 8) | (div << 4);
  445. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  446. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
  447. time_out = 20;
  448. value = PRSSTAT_SDSTB;
  449. while (!(esdhc_read32(&regs->prsstat) & value)) {
  450. if (time_out == 0) {
  451. printf("fsl_esdhc: Internal clock never stabilised.\n");
  452. break;
  453. }
  454. time_out--;
  455. mdelay(1);
  456. }
  457. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  458. }
  459. #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  460. static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
  461. {
  462. struct fsl_esdhc *regs = priv->esdhc_regs;
  463. u32 value;
  464. u32 time_out;
  465. value = esdhc_read32(&regs->sysctl);
  466. if (enable)
  467. value |= SYSCTL_CKEN;
  468. else
  469. value &= ~SYSCTL_CKEN;
  470. esdhc_write32(&regs->sysctl, value);
  471. time_out = 20;
  472. value = PRSSTAT_SDSTB;
  473. while (!(esdhc_read32(&regs->prsstat) & value)) {
  474. if (time_out == 0) {
  475. printf("fsl_esdhc: Internal clock never stabilised.\n");
  476. break;
  477. }
  478. time_out--;
  479. mdelay(1);
  480. }
  481. }
  482. #endif
  483. static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  484. {
  485. struct fsl_esdhc *regs = priv->esdhc_regs;
  486. #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  487. /* Select to use peripheral clock */
  488. esdhc_clock_control(priv, false);
  489. esdhc_setbits32(&regs->esdhcctl, ESDHCCTL_PCS);
  490. esdhc_clock_control(priv, true);
  491. #endif
  492. /* Set the clock speed */
  493. if (priv->clock != mmc->clock)
  494. set_sysctl(priv, mmc, mmc->clock);
  495. /* Set the bus width */
  496. esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
  497. if (mmc->bus_width == 4)
  498. esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
  499. else if (mmc->bus_width == 8)
  500. esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
  501. return 0;
  502. }
  503. static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  504. {
  505. struct fsl_esdhc *regs = priv->esdhc_regs;
  506. ulong start;
  507. /* Reset the entire host controller */
  508. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  509. /* Wait until the controller is available */
  510. start = get_timer(0);
  511. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  512. if (get_timer(start) > 1000)
  513. return -ETIMEDOUT;
  514. }
  515. /* Enable cache snooping */
  516. esdhc_write32(&regs->esdhcctl, 0x00000040);
  517. esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
  518. /* Set the initial clock speed */
  519. mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
  520. /* Disable the BRR and BWR bits in IRQSTAT */
  521. esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
  522. /* Put the PROCTL reg back to the default */
  523. esdhc_write32(&regs->proctl, PROCTL_INIT);
  524. /* Set timout to the maximum value */
  525. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
  526. return 0;
  527. }
  528. static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
  529. {
  530. struct fsl_esdhc *regs = priv->esdhc_regs;
  531. int timeout = 1000;
  532. #ifdef CONFIG_ESDHC_DETECT_QUIRK
  533. if (CONFIG_ESDHC_DETECT_QUIRK)
  534. return 1;
  535. #endif
  536. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
  537. udelay(1000);
  538. return timeout > 0;
  539. }
  540. #if !CONFIG_IS_ENABLED(DM_MMC)
  541. static int esdhc_getcd(struct mmc *mmc)
  542. {
  543. struct fsl_esdhc_priv *priv = mmc->priv;
  544. return esdhc_getcd_common(priv);
  545. }
  546. static int esdhc_init(struct mmc *mmc)
  547. {
  548. struct fsl_esdhc_priv *priv = mmc->priv;
  549. return esdhc_init_common(priv, mmc);
  550. }
  551. static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  552. struct mmc_data *data)
  553. {
  554. struct fsl_esdhc_priv *priv = mmc->priv;
  555. return esdhc_send_cmd_common(priv, mmc, cmd, data);
  556. }
  557. static int esdhc_set_ios(struct mmc *mmc)
  558. {
  559. struct fsl_esdhc_priv *priv = mmc->priv;
  560. return esdhc_set_ios_common(priv, mmc);
  561. }
  562. static const struct mmc_ops esdhc_ops = {
  563. .getcd = esdhc_getcd,
  564. .init = esdhc_init,
  565. .send_cmd = esdhc_send_cmd,
  566. .set_ios = esdhc_set_ios,
  567. };
  568. #endif
  569. static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
  570. struct mmc_config *cfg)
  571. {
  572. struct fsl_esdhc *regs = priv->esdhc_regs;
  573. u32 caps;
  574. caps = esdhc_read32(&regs->hostcapblt);
  575. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
  576. caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
  577. #endif
  578. #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  579. caps |= HOSTCAPBLT_VS33;
  580. #endif
  581. if (caps & HOSTCAPBLT_VS18)
  582. cfg->voltages |= MMC_VDD_165_195;
  583. if (caps & HOSTCAPBLT_VS30)
  584. cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
  585. if (caps & HOSTCAPBLT_VS33)
  586. cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
  587. cfg->name = "FSL_SDHC";
  588. if (caps & HOSTCAPBLT_HSS)
  589. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  590. cfg->f_min = 400000;
  591. cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
  592. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  593. }
  594. #if !CONFIG_IS_ENABLED(DM_MMC)
  595. int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
  596. {
  597. struct fsl_esdhc_plat *plat;
  598. struct fsl_esdhc_priv *priv;
  599. struct mmc_config *mmc_cfg;
  600. struct mmc *mmc;
  601. if (!cfg)
  602. return -EINVAL;
  603. priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
  604. if (!priv)
  605. return -ENOMEM;
  606. plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
  607. if (!plat) {
  608. free(priv);
  609. return -ENOMEM;
  610. }
  611. priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
  612. priv->sdhc_clk = cfg->sdhc_clk;
  613. mmc_cfg = &plat->cfg;
  614. if (cfg->max_bus_width == 8) {
  615. mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
  616. MMC_MODE_8BIT;
  617. } else if (cfg->max_bus_width == 4) {
  618. mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
  619. } else if (cfg->max_bus_width == 1) {
  620. mmc_cfg->host_caps |= MMC_MODE_1BIT;
  621. } else {
  622. mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
  623. MMC_MODE_8BIT;
  624. printf("No max bus width provided. Assume 8-bit supported.\n");
  625. }
  626. #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
  627. if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
  628. mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
  629. #endif
  630. mmc_cfg->ops = &esdhc_ops;
  631. fsl_esdhc_get_cfg_common(priv, mmc_cfg);
  632. mmc = mmc_create(mmc_cfg, priv);
  633. if (!mmc)
  634. return -EIO;
  635. priv->mmc = mmc;
  636. return 0;
  637. }
  638. int fsl_esdhc_mmc_init(bd_t *bis)
  639. {
  640. struct fsl_esdhc_cfg *cfg;
  641. cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
  642. cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
  643. cfg->sdhc_clk = gd->arch.sdhc_clk;
  644. return fsl_esdhc_initialize(bis, cfg);
  645. }
  646. #endif
  647. #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  648. void mmc_adapter_card_type_ident(void)
  649. {
  650. u8 card_id;
  651. u8 value;
  652. card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
  653. gd->arch.sdhc_adapter = card_id;
  654. switch (card_id) {
  655. case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
  656. value = QIXIS_READ(brdcfg[5]);
  657. value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
  658. QIXIS_WRITE(brdcfg[5], value);
  659. break;
  660. case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
  661. value = QIXIS_READ(pwr_ctl[1]);
  662. value |= QIXIS_EVDD_BY_SDHC_VS;
  663. QIXIS_WRITE(pwr_ctl[1], value);
  664. break;
  665. case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
  666. value = QIXIS_READ(brdcfg[5]);
  667. value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
  668. QIXIS_WRITE(brdcfg[5], value);
  669. break;
  670. case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
  671. break;
  672. case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
  673. break;
  674. case QIXIS_ESDHC_ADAPTER_TYPE_SD:
  675. break;
  676. case QIXIS_ESDHC_NO_ADAPTER:
  677. break;
  678. default:
  679. break;
  680. }
  681. }
  682. #endif
  683. #ifdef CONFIG_OF_LIBFDT
  684. __weak int esdhc_status_fixup(void *blob, const char *compat)
  685. {
  686. #ifdef CONFIG_FSL_ESDHC_PIN_MUX
  687. if (!hwconfig("esdhc")) {
  688. do_fixup_by_compat(blob, compat, "status", "disabled",
  689. sizeof("disabled"), 1);
  690. return 1;
  691. }
  692. #endif
  693. return 0;
  694. }
  695. void fdt_fixup_esdhc(void *blob, bd_t *bd)
  696. {
  697. const char *compat = "fsl,esdhc";
  698. if (esdhc_status_fixup(blob, compat))
  699. return;
  700. #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  701. do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
  702. gd->arch.sdhc_clk, 1);
  703. #else
  704. do_fixup_by_compat_u32(blob, compat, "clock-frequency",
  705. gd->arch.sdhc_clk, 1);
  706. #endif
  707. #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  708. do_fixup_by_compat_u32(blob, compat, "adapter-type",
  709. (u32)(gd->arch.sdhc_adapter), 1);
  710. #endif
  711. }
  712. #endif
  713. #if CONFIG_IS_ENABLED(DM_MMC)
  714. #ifndef CONFIG_PPC
  715. #include <asm/arch/clock.h>
  716. #endif
  717. static int fsl_esdhc_probe(struct udevice *dev)
  718. {
  719. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  720. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  721. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  722. fdt_addr_t addr;
  723. struct mmc *mmc;
  724. int ret;
  725. addr = dev_read_addr(dev);
  726. if (addr == FDT_ADDR_T_NONE)
  727. return -EINVAL;
  728. #ifdef CONFIG_PPC
  729. priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
  730. #else
  731. priv->esdhc_regs = (struct fsl_esdhc *)addr;
  732. #endif
  733. priv->dev = dev;
  734. if (IS_ENABLED(CONFIG_CLK)) {
  735. /* Assigned clock already set clock */
  736. ret = clk_get_by_name(dev, "per", &priv->per_clk);
  737. if (ret) {
  738. printf("Failed to get per_clk\n");
  739. return ret;
  740. }
  741. ret = clk_enable(&priv->per_clk);
  742. if (ret) {
  743. printf("Failed to enable per_clk\n");
  744. return ret;
  745. }
  746. priv->sdhc_clk = clk_get_rate(&priv->per_clk);
  747. } else {
  748. #ifndef CONFIG_PPC
  749. priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
  750. #else
  751. priv->sdhc_clk = gd->arch.sdhc_clk;
  752. #endif
  753. if (priv->sdhc_clk <= 0) {
  754. dev_err(dev, "Unable to get clk for %s\n", dev->name);
  755. return -EINVAL;
  756. }
  757. }
  758. fsl_esdhc_get_cfg_common(priv, &plat->cfg);
  759. mmc_of_parse(dev, &plat->cfg);
  760. mmc = &plat->mmc;
  761. mmc->cfg = &plat->cfg;
  762. mmc->dev = dev;
  763. upriv->mmc = mmc;
  764. return esdhc_init_common(priv, mmc);
  765. }
  766. static int fsl_esdhc_get_cd(struct udevice *dev)
  767. {
  768. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  769. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  770. if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
  771. return 1;
  772. return esdhc_getcd_common(priv);
  773. }
  774. static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  775. struct mmc_data *data)
  776. {
  777. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  778. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  779. return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
  780. }
  781. static int fsl_esdhc_set_ios(struct udevice *dev)
  782. {
  783. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  784. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  785. return esdhc_set_ios_common(priv, &plat->mmc);
  786. }
  787. static const struct dm_mmc_ops fsl_esdhc_ops = {
  788. .get_cd = fsl_esdhc_get_cd,
  789. .send_cmd = fsl_esdhc_send_cmd,
  790. .set_ios = fsl_esdhc_set_ios,
  791. #ifdef MMC_SUPPORTS_TUNING
  792. .execute_tuning = fsl_esdhc_execute_tuning,
  793. #endif
  794. };
  795. static const struct udevice_id fsl_esdhc_ids[] = {
  796. { .compatible = "fsl,esdhc", },
  797. { /* sentinel */ }
  798. };
  799. static int fsl_esdhc_bind(struct udevice *dev)
  800. {
  801. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  802. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  803. }
  804. U_BOOT_DRIVER(fsl_esdhc) = {
  805. .name = "fsl-esdhc-mmc",
  806. .id = UCLASS_MMC,
  807. .of_match = fsl_esdhc_ids,
  808. .ops = &fsl_esdhc_ops,
  809. .bind = fsl_esdhc_bind,
  810. .probe = fsl_esdhc_probe,
  811. .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
  812. .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
  813. };
  814. #endif