tsec.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale Three Speed Ethernet Controller driver
  4. *
  5. * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
  6. * (C) Copyright 2003, Motorola, Inc.
  7. * author Andy Fleming
  8. */
  9. #include <config.h>
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <net.h>
  14. #include <command.h>
  15. #include <tsec.h>
  16. #include <fsl_mdio.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <asm/processor.h>
  21. #include <asm/io.h>
  22. #ifndef CONFIG_DM_ETH
  23. /* Default initializations for TSEC controllers. */
  24. static struct tsec_info_struct tsec_info[] = {
  25. #ifdef CONFIG_TSEC1
  26. STD_TSEC_INFO(1), /* TSEC1 */
  27. #endif
  28. #ifdef CONFIG_TSEC2
  29. STD_TSEC_INFO(2), /* TSEC2 */
  30. #endif
  31. #ifdef CONFIG_MPC85XX_FEC
  32. {
  33. .regs = TSEC_GET_REGS(2, 0x2000),
  34. .devname = CONFIG_MPC85XX_FEC_NAME,
  35. .phyaddr = FEC_PHY_ADDR,
  36. .flags = FEC_FLAGS,
  37. .mii_devname = DEFAULT_MII_NAME
  38. }, /* FEC */
  39. #endif
  40. #ifdef CONFIG_TSEC3
  41. STD_TSEC_INFO(3), /* TSEC3 */
  42. #endif
  43. #ifdef CONFIG_TSEC4
  44. STD_TSEC_INFO(4), /* TSEC4 */
  45. #endif
  46. };
  47. #endif /* CONFIG_DM_ETH */
  48. #define TBIANA_SETTINGS ( \
  49. TBIANA_ASYMMETRIC_PAUSE \
  50. | TBIANA_SYMMETRIC_PAUSE \
  51. | TBIANA_FULL_DUPLEX \
  52. )
  53. /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
  54. #ifndef CONFIG_TSEC_TBICR_SETTINGS
  55. #define CONFIG_TSEC_TBICR_SETTINGS ( \
  56. TBICR_PHY_RESET \
  57. | TBICR_ANEG_ENABLE \
  58. | TBICR_FULL_DUPLEX \
  59. | TBICR_SPEED1_SET \
  60. )
  61. #endif /* CONFIG_TSEC_TBICR_SETTINGS */
  62. /* Configure the TBI for SGMII operation */
  63. static void tsec_configure_serdes(struct tsec_private *priv)
  64. {
  65. /*
  66. * Access TBI PHY registers at given TSEC register offset as opposed
  67. * to the register offset used for external PHY accesses
  68. */
  69. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  70. 0, TBI_ANA, TBIANA_SETTINGS);
  71. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  72. 0, TBI_TBICON, TBICON_CLK_SELECT);
  73. tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
  74. 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
  75. }
  76. /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
  77. * and this is the ethernet-crc method needed for TSEC -- and perhaps
  78. * some other adapter -- hash tables
  79. */
  80. #define CRCPOLY_LE 0xedb88320
  81. static u32 ether_crc(size_t len, unsigned char const *p)
  82. {
  83. int i;
  84. u32 crc;
  85. crc = ~0;
  86. while (len--) {
  87. crc ^= *p++;
  88. for (i = 0; i < 8; i++)
  89. crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
  90. }
  91. /* an reverse the bits, cuz of way they arrive -- last-first */
  92. crc = (crc >> 16) | (crc << 16);
  93. crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
  94. crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
  95. crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
  96. crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
  97. return crc;
  98. }
  99. /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
  100. /* Set the appropriate hash bit for the given addr */
  101. /*
  102. * The algorithm works like so:
  103. * 1) Take the Destination Address (ie the multicast address), and
  104. * do a CRC on it (little endian), and reverse the bits of the
  105. * result.
  106. * 2) Use the 8 most significant bits as a hash into a 256-entry
  107. * table. The table is controlled through 8 32-bit registers:
  108. * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
  109. * 255. This means that the 3 most significant bits in the
  110. * hash index which gaddr register to use, and the 5 other bits
  111. * indicate which bit (assuming an IBM numbering scheme, which
  112. * for PowerPC (tm) is usually the case) in the register holds
  113. * the entry.
  114. */
  115. #ifndef CONFIG_DM_ETH
  116. static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
  117. int join)
  118. #else
  119. static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
  120. #endif
  121. {
  122. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  123. struct tsec __iomem *regs = priv->regs;
  124. u32 result, value;
  125. u8 whichbit, whichreg;
  126. result = ether_crc(MAC_ADDR_LEN, mcast_mac);
  127. whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
  128. whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
  129. value = BIT(31 - whichbit);
  130. if (join)
  131. setbits_be32(&regs->hash.gaddr0 + whichreg, value);
  132. else
  133. clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
  134. return 0;
  135. }
  136. /*
  137. * Initialized required registers to appropriate values, zeroing
  138. * those we don't care about (unless zero is bad, in which case,
  139. * choose a more appropriate value)
  140. */
  141. static void init_registers(struct tsec __iomem *regs)
  142. {
  143. /* Clear IEVENT */
  144. out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
  145. out_be32(&regs->imask, IMASK_INIT_CLEAR);
  146. out_be32(&regs->hash.iaddr0, 0);
  147. out_be32(&regs->hash.iaddr1, 0);
  148. out_be32(&regs->hash.iaddr2, 0);
  149. out_be32(&regs->hash.iaddr3, 0);
  150. out_be32(&regs->hash.iaddr4, 0);
  151. out_be32(&regs->hash.iaddr5, 0);
  152. out_be32(&regs->hash.iaddr6, 0);
  153. out_be32(&regs->hash.iaddr7, 0);
  154. out_be32(&regs->hash.gaddr0, 0);
  155. out_be32(&regs->hash.gaddr1, 0);
  156. out_be32(&regs->hash.gaddr2, 0);
  157. out_be32(&regs->hash.gaddr3, 0);
  158. out_be32(&regs->hash.gaddr4, 0);
  159. out_be32(&regs->hash.gaddr5, 0);
  160. out_be32(&regs->hash.gaddr6, 0);
  161. out_be32(&regs->hash.gaddr7, 0);
  162. out_be32(&regs->rctrl, 0x00000000);
  163. /* Init RMON mib registers */
  164. memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
  165. out_be32(&regs->rmon.cam1, 0xffffffff);
  166. out_be32(&regs->rmon.cam2, 0xffffffff);
  167. out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
  168. out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
  169. out_be32(&regs->attr, ATTR_INIT_SETTINGS);
  170. out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
  171. }
  172. /*
  173. * Configure maccfg2 based on negotiated speed and duplex
  174. * reported by PHY handling code
  175. */
  176. static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
  177. {
  178. struct tsec __iomem *regs = priv->regs;
  179. u32 ecntrl, maccfg2;
  180. if (!phydev->link) {
  181. printf("%s: No link.\n", phydev->dev->name);
  182. return;
  183. }
  184. /* clear all bits relative with interface mode */
  185. ecntrl = in_be32(&regs->ecntrl);
  186. ecntrl &= ~ECNTRL_R100;
  187. maccfg2 = in_be32(&regs->maccfg2);
  188. maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
  189. if (phydev->duplex)
  190. maccfg2 |= MACCFG2_FULL_DUPLEX;
  191. switch (phydev->speed) {
  192. case 1000:
  193. maccfg2 |= MACCFG2_GMII;
  194. break;
  195. case 100:
  196. case 10:
  197. maccfg2 |= MACCFG2_MII;
  198. /*
  199. * Set R100 bit in all modes although
  200. * it is only used in RGMII mode
  201. */
  202. if (phydev->speed == 100)
  203. ecntrl |= ECNTRL_R100;
  204. break;
  205. default:
  206. printf("%s: Speed was bad\n", phydev->dev->name);
  207. break;
  208. }
  209. out_be32(&regs->ecntrl, ecntrl);
  210. out_be32(&regs->maccfg2, maccfg2);
  211. printf("Speed: %d, %s duplex%s\n", phydev->speed,
  212. (phydev->duplex) ? "full" : "half",
  213. (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
  214. }
  215. /*
  216. * This returns the status bits of the device. The return value
  217. * is never checked, and this is what the 8260 driver did, so we
  218. * do the same. Presumably, this would be zero if there were no
  219. * errors
  220. */
  221. #ifndef CONFIG_DM_ETH
  222. static int tsec_send(struct eth_device *dev, void *packet, int length)
  223. #else
  224. static int tsec_send(struct udevice *dev, void *packet, int length)
  225. #endif
  226. {
  227. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  228. struct tsec __iomem *regs = priv->regs;
  229. int result = 0;
  230. u16 status;
  231. int i;
  232. /* Find an empty buffer descriptor */
  233. for (i = 0;
  234. in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
  235. i++) {
  236. if (i >= TOUT_LOOP) {
  237. printf("%s: tsec: tx buffers full\n", dev->name);
  238. return result;
  239. }
  240. }
  241. out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
  242. out_be16(&priv->txbd[priv->tx_idx].length, length);
  243. status = in_be16(&priv->txbd[priv->tx_idx].status);
  244. out_be16(&priv->txbd[priv->tx_idx].status, status |
  245. (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
  246. /* Tell the DMA to go */
  247. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  248. /* Wait for buffer to be transmitted */
  249. for (i = 0;
  250. in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
  251. i++) {
  252. if (i >= TOUT_LOOP) {
  253. printf("%s: tsec: tx error\n", dev->name);
  254. return result;
  255. }
  256. }
  257. priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
  258. result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
  259. return result;
  260. }
  261. #ifndef CONFIG_DM_ETH
  262. static int tsec_recv(struct eth_device *dev)
  263. {
  264. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  265. struct tsec __iomem *regs = priv->regs;
  266. while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
  267. int length = in_be16(&priv->rxbd[priv->rx_idx].length);
  268. u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
  269. uchar *packet = net_rx_packets[priv->rx_idx];
  270. /* Send the packet up if there were no errors */
  271. if (!(status & RXBD_STATS))
  272. net_process_received_packet(packet, length - 4);
  273. else
  274. printf("Got error %x\n", (status & RXBD_STATS));
  275. out_be16(&priv->rxbd[priv->rx_idx].length, 0);
  276. status = RXBD_EMPTY;
  277. /* Set the wrap bit if this is the last element in the list */
  278. if ((priv->rx_idx + 1) == PKTBUFSRX)
  279. status |= RXBD_WRAP;
  280. out_be16(&priv->rxbd[priv->rx_idx].status, status);
  281. priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
  282. }
  283. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  284. out_be32(&regs->ievent, IEVENT_BSY);
  285. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  286. }
  287. return -1;
  288. }
  289. #else
  290. static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
  291. {
  292. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  293. struct tsec __iomem *regs = priv->regs;
  294. int ret = -1;
  295. if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
  296. int length = in_be16(&priv->rxbd[priv->rx_idx].length);
  297. u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
  298. u32 buf;
  299. /* Send the packet up if there were no errors */
  300. if (!(status & RXBD_STATS)) {
  301. buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
  302. *packetp = (uchar *)buf;
  303. ret = length - 4;
  304. } else {
  305. printf("Got error %x\n", (status & RXBD_STATS));
  306. }
  307. }
  308. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  309. out_be32(&regs->ievent, IEVENT_BSY);
  310. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  311. }
  312. return ret;
  313. }
  314. static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
  315. {
  316. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  317. u16 status;
  318. out_be16(&priv->rxbd[priv->rx_idx].length, 0);
  319. status = RXBD_EMPTY;
  320. /* Set the wrap bit if this is the last element in the list */
  321. if ((priv->rx_idx + 1) == PKTBUFSRX)
  322. status |= RXBD_WRAP;
  323. out_be16(&priv->rxbd[priv->rx_idx].status, status);
  324. priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
  325. return 0;
  326. }
  327. #endif
  328. /* Stop the interface */
  329. #ifndef CONFIG_DM_ETH
  330. static void tsec_halt(struct eth_device *dev)
  331. #else
  332. static void tsec_halt(struct udevice *dev)
  333. #endif
  334. {
  335. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  336. struct tsec __iomem *regs = priv->regs;
  337. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  338. setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  339. while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
  340. != (IEVENT_GRSC | IEVENT_GTSC))
  341. ;
  342. clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
  343. /* Shut down the PHY, as needed */
  344. phy_shutdown(priv->phydev);
  345. }
  346. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  347. /*
  348. * When MACCFG1[Rx_EN] is enabled during system boot as part
  349. * of the eTSEC port initialization sequence,
  350. * the eTSEC Rx logic may not be properly initialized.
  351. */
  352. void redundant_init(struct tsec_private *priv)
  353. {
  354. struct tsec __iomem *regs = priv->regs;
  355. uint t, count = 0;
  356. int fail = 1;
  357. static const u8 pkt[] = {
  358. 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
  359. 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
  360. 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
  361. 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
  362. 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
  363. 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
  364. 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
  365. 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
  366. 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
  367. 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
  368. 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
  369. 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
  370. 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
  371. 0x71, 0x72};
  372. /* Enable promiscuous mode */
  373. setbits_be32(&regs->rctrl, 0x8);
  374. /* Enable loopback mode */
  375. setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
  376. /* Enable transmit and receive */
  377. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  378. /* Tell the DMA it is clear to go */
  379. setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
  380. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  381. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  382. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  383. do {
  384. u16 status;
  385. tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
  386. /* Wait for buffer to be received */
  387. for (t = 0;
  388. in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
  389. t++) {
  390. if (t >= 10 * TOUT_LOOP) {
  391. printf("%s: tsec: rx error\n", priv->dev->name);
  392. break;
  393. }
  394. }
  395. if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
  396. fail = 0;
  397. out_be16(&priv->rxbd[priv->rx_idx].length, 0);
  398. status = RXBD_EMPTY;
  399. if ((priv->rx_idx + 1) == PKTBUFSRX)
  400. status |= RXBD_WRAP;
  401. out_be16(&priv->rxbd[priv->rx_idx].status, status);
  402. priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
  403. if (in_be32(&regs->ievent) & IEVENT_BSY) {
  404. out_be32(&regs->ievent, IEVENT_BSY);
  405. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  406. }
  407. if (fail) {
  408. printf("loopback recv packet error!\n");
  409. clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
  410. udelay(1000);
  411. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
  412. }
  413. } while ((count++ < 4) && (fail == 1));
  414. if (fail)
  415. panic("eTSEC init fail!\n");
  416. /* Disable promiscuous mode */
  417. clrbits_be32(&regs->rctrl, 0x8);
  418. /* Disable loopback mode */
  419. clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
  420. }
  421. #endif
  422. /*
  423. * Set up the buffers and their descriptors, and bring up the
  424. * interface
  425. */
  426. static void startup_tsec(struct tsec_private *priv)
  427. {
  428. struct tsec __iomem *regs = priv->regs;
  429. u16 status;
  430. int i;
  431. /* reset the indices to zero */
  432. priv->rx_idx = 0;
  433. priv->tx_idx = 0;
  434. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  435. uint svr;
  436. #endif
  437. /* Point to the buffer descriptors */
  438. out_be32(&regs->tbase, (u32)&priv->txbd[0]);
  439. out_be32(&regs->rbase, (u32)&priv->rxbd[0]);
  440. /* Initialize the Rx Buffer descriptors */
  441. for (i = 0; i < PKTBUFSRX; i++) {
  442. out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
  443. out_be16(&priv->rxbd[i].length, 0);
  444. out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
  445. }
  446. status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
  447. out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
  448. /* Initialize the TX Buffer Descriptors */
  449. for (i = 0; i < TX_BUF_CNT; i++) {
  450. out_be16(&priv->txbd[i].status, 0);
  451. out_be16(&priv->txbd[i].length, 0);
  452. out_be32(&priv->txbd[i].bufptr, 0);
  453. }
  454. status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
  455. out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
  456. #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  457. svr = get_svr();
  458. if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
  459. redundant_init(priv);
  460. #endif
  461. /* Enable Transmit and Receive */
  462. setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
  463. /* Tell the DMA it is clear to go */
  464. setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
  465. out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
  466. out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
  467. clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
  468. }
  469. /*
  470. * Initializes data structures and registers for the controller,
  471. * and brings the interface up. Returns the link status, meaning
  472. * that it returns success if the link is up, failure otherwise.
  473. * This allows U-Boot to find the first active controller.
  474. */
  475. #ifndef CONFIG_DM_ETH
  476. static int tsec_init(struct eth_device *dev, bd_t *bd)
  477. #else
  478. static int tsec_init(struct udevice *dev)
  479. #endif
  480. {
  481. struct tsec_private *priv = (struct tsec_private *)dev->priv;
  482. #ifdef CONFIG_DM_ETH
  483. struct eth_pdata *pdata = dev_get_platdata(dev);
  484. #else
  485. struct eth_device *pdata = dev;
  486. #endif
  487. struct tsec __iomem *regs = priv->regs;
  488. u32 tempval;
  489. int ret;
  490. /* Make sure the controller is stopped */
  491. tsec_halt(dev);
  492. /* Init MACCFG2. Defaults to GMII */
  493. out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
  494. /* Init ECNTRL */
  495. out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
  496. /*
  497. * Copy the station address into the address registers.
  498. * For a station address of 0x12345678ABCD in transmission
  499. * order (BE), MACnADDR1 is set to 0xCDAB7856 and
  500. * MACnADDR2 is set to 0x34120000.
  501. */
  502. tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
  503. (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
  504. out_be32(&regs->macstnaddr1, tempval);
  505. tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
  506. out_be32(&regs->macstnaddr2, tempval);
  507. /* Clear out (for the most part) the other registers */
  508. init_registers(regs);
  509. /* Ready the device for tx/rx */
  510. startup_tsec(priv);
  511. /* Start up the PHY */
  512. ret = phy_startup(priv->phydev);
  513. if (ret) {
  514. printf("Could not initialize PHY %s\n",
  515. priv->phydev->dev->name);
  516. return ret;
  517. }
  518. adjust_link(priv, priv->phydev);
  519. /* If there's no link, fail */
  520. return priv->phydev->link ? 0 : -1;
  521. }
  522. static phy_interface_t tsec_get_interface(struct tsec_private *priv)
  523. {
  524. struct tsec __iomem *regs = priv->regs;
  525. u32 ecntrl;
  526. ecntrl = in_be32(&regs->ecntrl);
  527. if (ecntrl & ECNTRL_SGMII_MODE)
  528. return PHY_INTERFACE_MODE_SGMII;
  529. if (ecntrl & ECNTRL_TBI_MODE) {
  530. if (ecntrl & ECNTRL_REDUCED_MODE)
  531. return PHY_INTERFACE_MODE_RTBI;
  532. else
  533. return PHY_INTERFACE_MODE_TBI;
  534. }
  535. if (ecntrl & ECNTRL_REDUCED_MODE) {
  536. phy_interface_t interface;
  537. if (ecntrl & ECNTRL_REDUCED_MII_MODE)
  538. return PHY_INTERFACE_MODE_RMII;
  539. interface = priv->interface;
  540. /*
  541. * This isn't autodetected, so it must
  542. * be set by the platform code.
  543. */
  544. if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
  545. interface == PHY_INTERFACE_MODE_RGMII_TXID ||
  546. interface == PHY_INTERFACE_MODE_RGMII_RXID)
  547. return interface;
  548. return PHY_INTERFACE_MODE_RGMII;
  549. }
  550. if (priv->flags & TSEC_GIGABIT)
  551. return PHY_INTERFACE_MODE_GMII;
  552. return PHY_INTERFACE_MODE_MII;
  553. }
  554. /*
  555. * Discover which PHY is attached to the device, and configure it
  556. * properly. If the PHY is not recognized, then return 0
  557. * (failure). Otherwise, return 1
  558. */
  559. static int init_phy(struct tsec_private *priv)
  560. {
  561. struct phy_device *phydev;
  562. struct tsec __iomem *regs = priv->regs;
  563. u32 supported = (SUPPORTED_10baseT_Half |
  564. SUPPORTED_10baseT_Full |
  565. SUPPORTED_100baseT_Half |
  566. SUPPORTED_100baseT_Full);
  567. if (priv->flags & TSEC_GIGABIT)
  568. supported |= SUPPORTED_1000baseT_Full;
  569. /* Assign a Physical address to the TBI */
  570. out_be32(&regs->tbipa, priv->tbiaddr);
  571. priv->interface = tsec_get_interface(priv);
  572. if (priv->interface == PHY_INTERFACE_MODE_SGMII)
  573. tsec_configure_serdes(priv);
  574. phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
  575. priv->interface);
  576. if (!phydev)
  577. return 0;
  578. phydev->supported &= supported;
  579. phydev->advertising = phydev->supported;
  580. priv->phydev = phydev;
  581. phy_config(phydev);
  582. return 1;
  583. }
  584. #ifndef CONFIG_DM_ETH
  585. /*
  586. * Initialize device structure. Returns success if PHY
  587. * initialization succeeded (i.e. if it recognizes the PHY)
  588. */
  589. static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
  590. {
  591. struct tsec_private *priv;
  592. struct eth_device *dev;
  593. int i;
  594. dev = (struct eth_device *)malloc(sizeof(*dev));
  595. if (!dev)
  596. return 0;
  597. memset(dev, 0, sizeof(*dev));
  598. priv = (struct tsec_private *)malloc(sizeof(*priv));
  599. if (!priv) {
  600. free(dev);
  601. return 0;
  602. }
  603. priv->regs = tsec_info->regs;
  604. priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
  605. priv->phyaddr = tsec_info->phyaddr;
  606. priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
  607. priv->flags = tsec_info->flags;
  608. strcpy(dev->name, tsec_info->devname);
  609. priv->interface = tsec_info->interface;
  610. priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
  611. priv->dev = dev;
  612. dev->iobase = 0;
  613. dev->priv = priv;
  614. dev->init = tsec_init;
  615. dev->halt = tsec_halt;
  616. dev->send = tsec_send;
  617. dev->recv = tsec_recv;
  618. dev->mcast = tsec_mcast_addr;
  619. /* Tell U-Boot to get the addr from the env */
  620. for (i = 0; i < 6; i++)
  621. dev->enetaddr[i] = 0;
  622. eth_register(dev);
  623. /* Reset the MAC */
  624. setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  625. udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
  626. clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  627. /* Try to initialize PHY here, and return */
  628. return init_phy(priv);
  629. }
  630. /*
  631. * Initialize all the TSEC devices
  632. *
  633. * Returns the number of TSEC devices that were initialized
  634. */
  635. int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
  636. {
  637. int i;
  638. int count = 0;
  639. for (i = 0; i < num; i++) {
  640. int ret = tsec_initialize(bis, &tsecs[i]);
  641. if (ret > 0)
  642. count += ret;
  643. }
  644. return count;
  645. }
  646. int tsec_standard_init(bd_t *bis)
  647. {
  648. struct fsl_pq_mdio_info info;
  649. info.regs = TSEC_GET_MDIO_REGS_BASE(1);
  650. info.name = DEFAULT_MII_NAME;
  651. fsl_pq_mdio_init(bis, &info);
  652. return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
  653. }
  654. #else /* CONFIG_DM_ETH */
  655. int tsec_probe(struct udevice *dev)
  656. {
  657. struct eth_pdata *pdata = dev_get_platdata(dev);
  658. struct tsec_private *priv = dev_get_priv(dev);
  659. struct tsec_mii_mng __iomem *ext_phyregs_mii;
  660. struct ofnode_phandle_args phandle_args;
  661. u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
  662. struct fsl_pq_mdio_info mdio_info;
  663. const char *phy_mode;
  664. fdt_addr_t reg;
  665. ofnode parent;
  666. int ret;
  667. pdata->iobase = (phys_addr_t)dev_read_addr(dev);
  668. priv->regs = dev_remap_addr(dev);
  669. if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
  670. &phandle_args)) {
  671. printf("phy-handle does not exist under tsec %s\n", dev->name);
  672. return -ENOENT;
  673. } else {
  674. int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
  675. priv->phyaddr = reg;
  676. }
  677. parent = ofnode_get_parent(phandle_args.node);
  678. if (!ofnode_valid(parent)) {
  679. printf("No parent node for PHY?\n");
  680. return -ENOENT;
  681. }
  682. reg = ofnode_get_addr_index(parent, 0);
  683. if (reg == FDT_ADDR_T_NONE) {
  684. printf("No 'reg' property of MII for external PHY\n");
  685. return -ENOENT;
  686. }
  687. ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
  688. MAP_NOCACHE);
  689. ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
  690. &phandle_args);
  691. if (ret == 0) {
  692. ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
  693. parent = ofnode_get_parent(phandle_args.node);
  694. if (!ofnode_valid(parent)) {
  695. printf("No parent node for TBI PHY?\n");
  696. return -ENOENT;
  697. }
  698. reg = ofnode_get_addr_index(parent, 0);
  699. if (reg == FDT_ADDR_T_NONE) {
  700. printf("No 'reg' property of MII for TBI PHY\n");
  701. return -ENOENT;
  702. }
  703. priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET,
  704. 0, MAP_NOCACHE);
  705. }
  706. priv->tbiaddr = tbiaddr;
  707. phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
  708. if (phy_mode)
  709. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  710. if (pdata->phy_interface == -1) {
  711. printf("Invalid PHY interface '%s'\n", phy_mode);
  712. return -EINVAL;
  713. }
  714. priv->interface = pdata->phy_interface;
  715. /* Initialize flags */
  716. priv->flags = TSEC_GIGABIT;
  717. if (priv->interface == PHY_INTERFACE_MODE_SGMII)
  718. priv->flags |= TSEC_SGMII;
  719. mdio_info.regs = ext_phyregs_mii;
  720. mdio_info.name = (char *)dev->name;
  721. ret = fsl_pq_mdio_init(NULL, &mdio_info);
  722. if (ret)
  723. return ret;
  724. /* Reset the MAC */
  725. setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  726. udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
  727. clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
  728. priv->dev = dev;
  729. priv->bus = miiphy_get_dev_by_name(dev->name);
  730. /* Try to initialize PHY here, and return */
  731. return !init_phy(priv);
  732. }
  733. int tsec_remove(struct udevice *dev)
  734. {
  735. struct tsec_private *priv = dev->priv;
  736. free(priv->phydev);
  737. mdio_unregister(priv->bus);
  738. mdio_free(priv->bus);
  739. return 0;
  740. }
  741. static const struct eth_ops tsec_ops = {
  742. .start = tsec_init,
  743. .send = tsec_send,
  744. .recv = tsec_recv,
  745. .free_pkt = tsec_free_pkt,
  746. .stop = tsec_halt,
  747. .mcast = tsec_mcast_addr,
  748. };
  749. static const struct udevice_id tsec_ids[] = {
  750. { .compatible = "fsl,etsec2" },
  751. { }
  752. };
  753. U_BOOT_DRIVER(eth_tsec) = {
  754. .name = "tsec",
  755. .id = UCLASS_ETH,
  756. .of_match = tsec_ids,
  757. .probe = tsec_probe,
  758. .remove = tsec_remove,
  759. .ops = &tsec_ops,
  760. .priv_auto_alloc_size = sizeof(struct tsec_private),
  761. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  762. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  763. };
  764. #endif /* CONFIG_DM_ETH */