t4240qds.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <env.h>
  9. #include <fdt_support.h>
  10. #include <i2c.h>
  11. #include <image.h>
  12. #include <init.h>
  13. #include <irq_func.h>
  14. #include <log.h>
  15. #include <netdev.h>
  16. #include <linux/compiler.h>
  17. #include <asm/mmu.h>
  18. #include <asm/processor.h>
  19. #include <asm/cache.h>
  20. #include <asm/immap_85xx.h>
  21. #include <asm/fsl_law.h>
  22. #include <asm/fsl_serdes.h>
  23. #include <asm/fsl_liodn.h>
  24. #include <fm_eth.h>
  25. #include <linux/delay.h>
  26. #include "../common/qixis.h"
  27. #include "../common/vsc3316_3308.h"
  28. #include "t4qds.h"
  29. #include "t4240qds_qixis.h"
  30. DECLARE_GLOBAL_DATA_PTR;
  31. static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
  32. {8, 8}, {9, 9}, {14, 14}, {15, 15} };
  33. static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
  34. {10, 10}, {11, 11}, {12, 12}, {13, 13} };
  35. static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
  36. {10, 11}, {11, 10}, {12, 2}, {13, 3} };
  37. static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
  38. {8, 9}, {9, 8}, {14, 1}, {15, 0} };
  39. int checkboard(void)
  40. {
  41. char buf[64];
  42. u8 sw;
  43. struct cpu_type *cpu = gd->arch.cpu;
  44. unsigned int i;
  45. printf("Board: %sQDS, ", cpu->name);
  46. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
  47. QIXIS_READ(id), QIXIS_READ(arch));
  48. sw = QIXIS_READ(brdcfg[0]);
  49. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  50. if (sw < 0x8)
  51. printf("vBank: %d\n", sw);
  52. else if (sw == 0x8)
  53. puts("Promjet\n");
  54. else if (sw == 0x9)
  55. puts("NAND\n");
  56. else
  57. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  58. printf("FPGA: v%d (%s), build %d",
  59. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  60. (int)qixis_read_minor());
  61. /* the timestamp string contains "\n" at the end */
  62. printf(" on %s", qixis_read_time(buf));
  63. /*
  64. * Display the actual SERDES reference clocks as configured by the
  65. * dip switches on the board. Note that the SWx registers could
  66. * technically be set to force the reference clocks to match the
  67. * values that the SERDES expects (or vice versa). For now, however,
  68. * we just display both values and hope the user notices when they
  69. * don't match.
  70. */
  71. puts("SERDES Reference Clocks: ");
  72. sw = QIXIS_READ(brdcfg[2]);
  73. for (i = 0; i < MAX_SERDES; i++) {
  74. static const char * const freq[] = {
  75. "100", "125", "156.25", "161.1328125"};
  76. unsigned int clock = (sw >> (6 - 2 * i)) & 3;
  77. printf("SERDES%u=%sMHz ", i+1, freq[clock]);
  78. }
  79. puts("\n");
  80. return 0;
  81. }
  82. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  83. {
  84. int ret;
  85. #ifdef CONFIG_DM_I2C
  86. struct udevice *dev;
  87. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  88. 1, &dev);
  89. if (ret) {
  90. printf("%s: Cannot find udev for a bus %d\n", __func__,
  91. bus_num);
  92. return ret;
  93. }
  94. ret = dm_i2c_write(dev, 0, &ch, 1);
  95. #else
  96. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  97. #endif
  98. if (ret) {
  99. puts("PCA: failed to select proper channel\n");
  100. return ret;
  101. }
  102. return 0;
  103. }
  104. /*
  105. * read_voltage from sensor on I2C bus
  106. * We use average of 4 readings, waiting for 532us befor another reading
  107. */
  108. #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
  109. #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
  110. static inline int read_voltage(void)
  111. {
  112. int i, ret, voltage_read = 0;
  113. u16 vol_mon;
  114. #ifdef CONFIG_DM_I2C
  115. struct udevice *dev;
  116. int bus_num = 0;
  117. #endif
  118. for (i = 0; i < NUM_READINGS; i++) {
  119. #ifdef CONFIG_DM_I2C
  120. ret = i2c_get_chip_for_busnum(bus_num, I2C_VOL_MONITOR_ADDR,
  121. 1, &dev);
  122. if (ret) {
  123. printf("%s: Cannot find udev for a bus %d\n", __func__,
  124. bus_num);
  125. return ret;
  126. }
  127. ret = dm_i2c_read(dev,
  128. I2C_VOL_MONITOR_BUS_V_OFFSET,
  129. (void *)&vol_mon, 2);
  130. #else
  131. ret = i2c_read(I2C_VOL_MONITOR_ADDR,
  132. I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
  133. #endif
  134. if (ret) {
  135. printf("VID: failed to read core voltage\n");
  136. return ret;
  137. }
  138. if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
  139. printf("VID: Core voltage sensor error\n");
  140. return -1;
  141. }
  142. debug("VID: bus voltage reads 0x%04x\n", vol_mon);
  143. /* LSB = 4mv */
  144. voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
  145. udelay(WAIT_FOR_ADC);
  146. }
  147. /* calculate the average */
  148. voltage_read /= NUM_READINGS;
  149. return voltage_read;
  150. }
  151. /*
  152. * We need to calculate how long before the voltage starts to drop or increase
  153. * It returns with the loop count. Each loop takes several readings (532us)
  154. */
  155. static inline int wait_for_voltage_change(int vdd_last)
  156. {
  157. int timeout, vdd_current;
  158. vdd_current = read_voltage();
  159. /* wait until voltage starts to drop */
  160. for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
  161. timeout < 100; timeout++) {
  162. vdd_current = read_voltage();
  163. }
  164. if (timeout >= 100) {
  165. printf("VID: Voltage adjustment timeout\n");
  166. return -1;
  167. }
  168. return timeout;
  169. }
  170. /*
  171. * argument 'wait' is the time we know the voltage difference can be measured
  172. * this function keeps reading the voltage until it is stable
  173. */
  174. static inline int wait_for_voltage_stable(int wait)
  175. {
  176. int timeout, vdd_current, vdd_last;
  177. vdd_last = read_voltage();
  178. udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
  179. /* wait until voltage is stable */
  180. vdd_current = read_voltage();
  181. for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
  182. timeout < 100; timeout++) {
  183. vdd_last = vdd_current;
  184. udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
  185. vdd_current = read_voltage();
  186. }
  187. if (timeout >= 100) {
  188. printf("VID: Voltage adjustment timeout\n");
  189. return -1;
  190. }
  191. return vdd_current;
  192. }
  193. static inline int set_voltage(u8 vid)
  194. {
  195. int wait, vdd_last;
  196. vdd_last = read_voltage();
  197. QIXIS_WRITE(brdcfg[6], vid);
  198. wait = wait_for_voltage_change(vdd_last);
  199. if (wait < 0)
  200. return -1;
  201. debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
  202. wait = wait ? wait : 1;
  203. vdd_last = wait_for_voltage_stable(wait);
  204. if (vdd_last < 0)
  205. return -1;
  206. debug("VID: Current voltage is %d mV\n", vdd_last);
  207. return vdd_last;
  208. }
  209. static int adjust_vdd(ulong vdd_override)
  210. {
  211. int re_enable = disable_interrupts();
  212. ccsr_gur_t __iomem *gur =
  213. (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  214. u32 fusesr;
  215. u8 vid, vid_current;
  216. int vdd_target, vdd_current, vdd_last;
  217. int ret;
  218. unsigned long vdd_string_override;
  219. char *vdd_string;
  220. static const uint16_t vdd[32] = {
  221. 0, /* unused */
  222. 9875, /* 0.9875V */
  223. 9750,
  224. 9625,
  225. 9500,
  226. 9375,
  227. 9250,
  228. 9125,
  229. 9000,
  230. 8875,
  231. 8750,
  232. 8625,
  233. 8500,
  234. 8375,
  235. 8250,
  236. 8125,
  237. 10000, /* 1.0000V */
  238. 10125,
  239. 10250,
  240. 10375,
  241. 10500,
  242. 10625,
  243. 10750,
  244. 10875,
  245. 11000,
  246. 0, /* reserved */
  247. };
  248. struct vdd_drive {
  249. u8 vid;
  250. unsigned voltage;
  251. };
  252. ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0);
  253. if (ret) {
  254. debug("VID: I2c failed to switch channel\n");
  255. ret = -1;
  256. goto exit;
  257. }
  258. /* get the voltage ID from fuse status register */
  259. fusesr = in_be32(&gur->dcfg_fusesr);
  260. vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
  261. FSL_CORENET_DCFG_FUSESR_VID_MASK;
  262. if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
  263. vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
  264. FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
  265. }
  266. vdd_target = vdd[vid];
  267. /* check override variable for overriding VDD */
  268. vdd_string = env_get("t4240qds_vdd_mv");
  269. if (vdd_override == 0 && vdd_string &&
  270. !strict_strtoul(vdd_string, 10, &vdd_string_override))
  271. vdd_override = vdd_string_override;
  272. if (vdd_override >= 819 && vdd_override <= 1212) {
  273. vdd_target = vdd_override * 10; /* convert to 1/10 mV */
  274. debug("VDD override is %lu\n", vdd_override);
  275. } else if (vdd_override != 0) {
  276. printf("Invalid value.\n");
  277. }
  278. if (vdd_target == 0) {
  279. debug("VID: VID not used\n");
  280. ret = 0;
  281. goto exit;
  282. } else {
  283. /* round up and divice by 10 to get a value in mV */
  284. vdd_target = DIV_ROUND_UP(vdd_target, 10);
  285. debug("VID: vid = %d mV\n", vdd_target);
  286. }
  287. /*
  288. * Check current board VID setting
  289. * Voltage regulator support output to 6.250mv step
  290. * The highes voltage allowed for this board is (vid=0x40) 1.21250V
  291. * the lowest is (vid=0x7f) 0.81875V
  292. */
  293. vid_current = QIXIS_READ(brdcfg[6]);
  294. vdd_current = 121250 - (vid_current - 0x40) * 625;
  295. debug("VID: Current vid setting is (0x%x) %d mV\n",
  296. vid_current, vdd_current/100);
  297. /*
  298. * Read voltage monitor to check real voltage.
  299. * Voltage monitor LSB is 4mv.
  300. */
  301. vdd_last = read_voltage();
  302. if (vdd_last < 0) {
  303. printf("VID: Could not read voltage sensor abort VID adjustment\n");
  304. ret = -1;
  305. goto exit;
  306. }
  307. debug("VID: Core voltage is at %d mV\n", vdd_last);
  308. /*
  309. * Adjust voltage to at or 8mV above target.
  310. * Each step of adjustment is 6.25mV.
  311. * Stepping down too fast may cause over current.
  312. */
  313. while (vdd_last > 0 && vid_current < 0x80 &&
  314. vdd_last > (vdd_target + 8)) {
  315. vid_current++;
  316. vdd_last = set_voltage(vid_current);
  317. }
  318. /*
  319. * Check if we need to step up
  320. * This happens when board voltage switch was set too low
  321. */
  322. while (vdd_last > 0 && vid_current >= 0x40 &&
  323. vdd_last < vdd_target + 2) {
  324. vid_current--;
  325. vdd_last = set_voltage(vid_current);
  326. }
  327. if (vdd_last > 0)
  328. printf("VID: Core voltage %d mV\n", vdd_last);
  329. else
  330. ret = -1;
  331. exit:
  332. if (re_enable)
  333. enable_interrupts();
  334. return ret;
  335. }
  336. /* Configure Crossbar switches for Front-Side SerDes Ports */
  337. int config_frontside_crossbar_vsc3316(void)
  338. {
  339. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  340. u32 srds_prtcl_s1, srds_prtcl_s2;
  341. int ret;
  342. ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS, 0);
  343. if (ret)
  344. return ret;
  345. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  346. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  347. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  348. switch (srds_prtcl_s1) {
  349. case 37:
  350. case 38:
  351. /* swap first lane and third lane on slot1 */
  352. vsc3316_fsm1_tx[0][1] = 14;
  353. vsc3316_fsm1_tx[6][1] = 0;
  354. vsc3316_fsm1_rx[1][1] = 2;
  355. vsc3316_fsm1_rx[6][1] = 13;
  356. case 39:
  357. case 40:
  358. case 45:
  359. case 46:
  360. case 47:
  361. case 48:
  362. /* swap first lane and third lane on slot2 */
  363. vsc3316_fsm1_tx[2][1] = 8;
  364. vsc3316_fsm1_tx[4][1] = 6;
  365. vsc3316_fsm1_rx[2][1] = 10;
  366. vsc3316_fsm1_rx[5][1] = 5;
  367. default:
  368. ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
  369. if (ret)
  370. return ret;
  371. ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
  372. if (ret)
  373. return ret;
  374. break;
  375. }
  376. srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  377. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  378. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  379. switch (srds_prtcl_s2) {
  380. case 37:
  381. case 38:
  382. /* swap first lane and third lane on slot3 */
  383. vsc3316_fsm2_tx[2][1] = 11;
  384. vsc3316_fsm2_tx[5][1] = 4;
  385. vsc3316_fsm2_rx[2][1] = 9;
  386. vsc3316_fsm2_rx[4][1] = 7;
  387. case 39:
  388. case 40:
  389. case 45:
  390. case 46:
  391. case 47:
  392. case 48:
  393. case 49:
  394. case 50:
  395. case 51:
  396. case 52:
  397. case 53:
  398. case 54:
  399. /* swap first lane and third lane on slot4 */
  400. vsc3316_fsm2_tx[6][1] = 3;
  401. vsc3316_fsm2_tx[1][1] = 12;
  402. vsc3316_fsm2_rx[0][1] = 1;
  403. vsc3316_fsm2_rx[6][1] = 15;
  404. default:
  405. ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
  406. if (ret)
  407. return ret;
  408. ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
  409. if (ret)
  410. return ret;
  411. break;
  412. }
  413. return 0;
  414. }
  415. int config_backside_crossbar_mux(void)
  416. {
  417. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  418. u32 srds_prtcl_s3, srds_prtcl_s4;
  419. u8 brdcfg;
  420. srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
  421. FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
  422. srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
  423. switch (srds_prtcl_s3) {
  424. case 0:
  425. /* SerDes3 is not enabled */
  426. break;
  427. case 1:
  428. case 2:
  429. case 9:
  430. case 10:
  431. /* SD3(0:7) => SLOT5(0:7) */
  432. brdcfg = QIXIS_READ(brdcfg[12]);
  433. brdcfg &= ~BRDCFG12_SD3MX_MASK;
  434. brdcfg |= BRDCFG12_SD3MX_SLOT5;
  435. QIXIS_WRITE(brdcfg[12], brdcfg);
  436. break;
  437. case 3:
  438. case 4:
  439. case 5:
  440. case 6:
  441. case 7:
  442. case 8:
  443. case 11:
  444. case 12:
  445. case 13:
  446. case 14:
  447. case 15:
  448. case 16:
  449. case 17:
  450. case 18:
  451. case 19:
  452. case 20:
  453. /* SD3(4:7) => SLOT6(0:3) */
  454. brdcfg = QIXIS_READ(brdcfg[12]);
  455. brdcfg &= ~BRDCFG12_SD3MX_MASK;
  456. brdcfg |= BRDCFG12_SD3MX_SLOT6;
  457. QIXIS_WRITE(brdcfg[12], brdcfg);
  458. break;
  459. default:
  460. printf("WARNING: unsupported for SerDes3 Protocol %d\n",
  461. srds_prtcl_s3);
  462. return -1;
  463. }
  464. srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
  465. FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
  466. srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
  467. switch (srds_prtcl_s4) {
  468. case 0:
  469. /* SerDes4 is not enabled */
  470. break;
  471. case 1:
  472. case 2:
  473. /* 10b, SD4(0:7) => SLOT7(0:7) */
  474. brdcfg = QIXIS_READ(brdcfg[12]);
  475. brdcfg &= ~BRDCFG12_SD4MX_MASK;
  476. brdcfg |= BRDCFG12_SD4MX_SLOT7;
  477. QIXIS_WRITE(brdcfg[12], brdcfg);
  478. break;
  479. case 3:
  480. case 4:
  481. case 5:
  482. case 6:
  483. case 7:
  484. case 8:
  485. /* x1b, SD4(4:7) => SLOT8(0:3) */
  486. brdcfg = QIXIS_READ(brdcfg[12]);
  487. brdcfg &= ~BRDCFG12_SD4MX_MASK;
  488. brdcfg |= BRDCFG12_SD4MX_SLOT8;
  489. QIXIS_WRITE(brdcfg[12], brdcfg);
  490. break;
  491. case 9:
  492. case 10:
  493. case 11:
  494. case 12:
  495. case 13:
  496. case 14:
  497. case 15:
  498. case 16:
  499. case 18:
  500. /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
  501. brdcfg = QIXIS_READ(brdcfg[12]);
  502. brdcfg &= ~BRDCFG12_SD4MX_MASK;
  503. brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
  504. QIXIS_WRITE(brdcfg[12], brdcfg);
  505. break;
  506. default:
  507. printf("WARNING: unsupported for SerDes4 Protocol %d\n",
  508. srds_prtcl_s4);
  509. return -1;
  510. }
  511. return 0;
  512. }
  513. int board_early_init_r(void)
  514. {
  515. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  516. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  517. /*
  518. * Remap Boot flash + PROMJET region to caching-inhibited
  519. * so that flash can be erased properly.
  520. */
  521. /* Flush d-cache and invalidate i-cache of any FLASH data */
  522. flush_dcache();
  523. invalidate_icache();
  524. if (flash_esel == -1) {
  525. /* very unlikely unless something is messed up */
  526. puts("Error: Could not find TLB for FLASH BASE\n");
  527. flash_esel = 2; /* give our best effort to continue */
  528. } else {
  529. /* invalidate existing TLB entry for flash + promjet */
  530. disable_tlb(flash_esel);
  531. }
  532. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  533. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  534. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  535. /* Disable remote I2C connection to qixis fpga */
  536. QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
  537. /*
  538. * Adjust core voltage according to voltage ID
  539. * This function changes I2C mux to channel 2.
  540. */
  541. if (adjust_vdd(0))
  542. printf("Warning: Adjusting core voltage failed.\n");
  543. /* Configure board SERDES ports crossbar */
  544. config_frontside_crossbar_vsc3316();
  545. config_backside_crossbar_mux();
  546. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  547. return 0;
  548. }
  549. unsigned long get_board_sys_clk(void)
  550. {
  551. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  552. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  553. /* use accurate clock measurement */
  554. int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
  555. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  556. u32 val;
  557. val = freq * base;
  558. if (val) {
  559. debug("SYS Clock measurement is: %d\n", val);
  560. return val;
  561. } else {
  562. printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
  563. }
  564. #endif
  565. switch (sysclk_conf & 0x0F) {
  566. case QIXIS_SYSCLK_83:
  567. return 83333333;
  568. case QIXIS_SYSCLK_100:
  569. return 100000000;
  570. case QIXIS_SYSCLK_125:
  571. return 125000000;
  572. case QIXIS_SYSCLK_133:
  573. return 133333333;
  574. case QIXIS_SYSCLK_150:
  575. return 150000000;
  576. case QIXIS_SYSCLK_160:
  577. return 160000000;
  578. case QIXIS_SYSCLK_166:
  579. return 166666666;
  580. }
  581. return 66666666;
  582. }
  583. unsigned long get_board_ddr_clk(void)
  584. {
  585. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  586. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  587. /* use accurate clock measurement */
  588. int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
  589. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  590. u32 val;
  591. val = freq * base;
  592. if (val) {
  593. debug("DDR Clock measurement is: %d\n", val);
  594. return val;
  595. } else {
  596. printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
  597. }
  598. #endif
  599. switch ((ddrclk_conf & 0x30) >> 4) {
  600. case QIXIS_DDRCLK_100:
  601. return 100000000;
  602. case QIXIS_DDRCLK_125:
  603. return 125000000;
  604. case QIXIS_DDRCLK_133:
  605. return 133333333;
  606. }
  607. return 66666666;
  608. }
  609. int misc_init_r(void)
  610. {
  611. u8 sw;
  612. void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  613. serdes_corenet_t *srds_regs;
  614. u32 actual[MAX_SERDES];
  615. u32 pllcr0, expected;
  616. unsigned int i;
  617. sw = QIXIS_READ(brdcfg[2]);
  618. for (i = 0; i < MAX_SERDES; i++) {
  619. unsigned int clock = (sw >> (6 - 2 * i)) & 3;
  620. switch (clock) {
  621. case 0:
  622. actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
  623. break;
  624. case 1:
  625. actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
  626. break;
  627. case 2:
  628. actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
  629. break;
  630. case 3:
  631. actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
  632. break;
  633. }
  634. }
  635. for (i = 0; i < MAX_SERDES; i++) {
  636. srds_regs = srds_base + i * 0x1000;
  637. pllcr0 = srds_regs->bank[0].pllcr0;
  638. expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
  639. if (expected != actual[i]) {
  640. printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
  641. i + 1, serdes_clock_to_string(expected),
  642. serdes_clock_to_string(actual[i]));
  643. }
  644. }
  645. return 0;
  646. }
  647. int ft_board_setup(void *blob, bd_t *bd)
  648. {
  649. phys_addr_t base;
  650. phys_size_t size;
  651. ft_cpu_setup(blob, bd);
  652. base = env_get_bootm_low();
  653. size = env_get_bootm_size();
  654. fdt_fixup_memory(blob, (u64)base, (u64)size);
  655. #ifdef CONFIG_PCI
  656. pci_of_setup(blob, bd);
  657. #endif
  658. fdt_fixup_liodn(blob);
  659. fsl_fdt_fixup_dr_usb(blob, bd);
  660. #ifdef CONFIG_SYS_DPAA_FMAN
  661. #ifndef CONFIG_DM_ETH
  662. fdt_fixup_fman_ethernet(blob);
  663. #endif
  664. fdt_fixup_board_enet(blob);
  665. #endif
  666. return 0;
  667. }
  668. /*
  669. * This function is called by bdinfo to print detail board information.
  670. * As an exmaple for future board, we organize the messages into
  671. * several sections. If applicable, the message is in the format of
  672. * <name> = <value>
  673. * It should aligned with normal output of bdinfo command.
  674. *
  675. * Voltage: Core, DDR and another configurable voltages
  676. * Clock : Critical clocks which are not printed already
  677. * RCW : RCW source if not printed already
  678. * Misc : Other important information not in above catagories
  679. */
  680. void board_detail(void)
  681. {
  682. int i;
  683. u8 brdcfg[16], dutcfg[16], rst_ctl;
  684. int vdd, rcwsrc;
  685. static const char * const clk[] = {"66.67", "100", "125", "133.33"};
  686. for (i = 0; i < 16; i++) {
  687. brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
  688. dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
  689. }
  690. /* Voltage secion */
  691. if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0)) {
  692. vdd = read_voltage();
  693. if (vdd > 0)
  694. printf("Core voltage= %d mV\n", vdd);
  695. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  696. }
  697. printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
  698. /* clock section */
  699. printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
  700. clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
  701. /* RCW section */
  702. rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
  703. puts("RCW source = ");
  704. switch (rcwsrc) {
  705. case 0x017:
  706. case 0x01f:
  707. puts("8-bit NOR\n");
  708. break;
  709. case 0x027:
  710. case 0x02F:
  711. puts("16-bit NOR\n");
  712. break;
  713. case 0x040:
  714. puts("SDHC/eMMC\n");
  715. break;
  716. case 0x044:
  717. puts("SPI 16-bit addressing\n");
  718. break;
  719. case 0x045:
  720. puts("SPI 24-bit addressing\n");
  721. break;
  722. case 0x048:
  723. puts("I2C normal addressing\n");
  724. break;
  725. case 0x049:
  726. puts("I2C extended addressing\n");
  727. break;
  728. case 0x108:
  729. case 0x109:
  730. case 0x10a:
  731. case 0x10b:
  732. puts("8-bit NAND, 2KB\n");
  733. break;
  734. default:
  735. if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
  736. puts("Hard-coded RCW\n");
  737. else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
  738. puts("8-bit NAND, 4KB\n");
  739. else
  740. puts("unknown\n");
  741. break;
  742. }
  743. /* Misc section */
  744. rst_ctl = QIXIS_READ(rst_ctl);
  745. puts("HRESET_REQ = ");
  746. switch (rst_ctl & 0x30) {
  747. case 0x00:
  748. puts("Ignored\n");
  749. break;
  750. case 0x10:
  751. puts("Assert HRESET\n");
  752. break;
  753. case 0x30:
  754. puts("Reset system\n");
  755. break;
  756. default:
  757. puts("N/A\n");
  758. break;
  759. }
  760. }
  761. /*
  762. * Reverse engineering switch settings.
  763. * Some bits cannot be figured out. They will be displayed as
  764. * underscore in binary format. mask[] has those bits.
  765. * Some bits are calculated differently than the actual switches
  766. * if booting with overriding by FPGA.
  767. */
  768. void qixis_dump_switch(void)
  769. {
  770. int i;
  771. u8 sw[9];
  772. /*
  773. * Any bit with 1 means that bit cannot be reverse engineered.
  774. * It will be displayed as _ in binary format.
  775. */
  776. static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
  777. char buf[10];
  778. u8 brdcfg[16], dutcfg[16];
  779. for (i = 0; i < 16; i++) {
  780. brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
  781. dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
  782. }
  783. sw[0] = dutcfg[0];
  784. sw[1] = (dutcfg[1] << 0x07) |
  785. ((dutcfg[12] & 0xC0) >> 1) |
  786. ((dutcfg[11] & 0xE0) >> 3) |
  787. ((dutcfg[6] & 0x80) >> 6) |
  788. ((dutcfg[1] & 0x80) >> 7);
  789. sw[2] = ((brdcfg[1] & 0x0f) << 4) |
  790. ((brdcfg[1] & 0x30) >> 2) |
  791. ((brdcfg[1] & 0x40) >> 5) |
  792. ((brdcfg[1] & 0x80) >> 7);
  793. sw[3] = brdcfg[2];
  794. sw[4] = ((dutcfg[2] & 0x01) << 7) |
  795. ((dutcfg[2] & 0x06) << 4) |
  796. ((~QIXIS_READ(present)) & 0x10) |
  797. ((brdcfg[3] & 0x80) >> 4) |
  798. ((brdcfg[3] & 0x01) << 2) |
  799. ((brdcfg[6] == 0x62) ? 3 :
  800. ((brdcfg[6] == 0x5a) ? 2 :
  801. ((brdcfg[6] == 0x5e) ? 1 : 0)));
  802. sw[5] = ((brdcfg[0] & 0x0f) << 4) |
  803. ((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
  804. ((brdcfg[0] & 0x40) >> 5);
  805. sw[6] = (brdcfg[11] & 0x20) |
  806. ((brdcfg[5] & 0x02) << 3);
  807. sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
  808. ((brdcfg[5] & 0x10) << 2);
  809. sw[8] = ((brdcfg[12] & 0x08) << 4) |
  810. ((brdcfg[12] & 0x03) << 5);
  811. puts("DIP switch (reverse-engineering)\n");
  812. for (i = 0; i < 9; i++) {
  813. printf("SW%d = 0b%s (0x%02x)\n",
  814. i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
  815. }
  816. }
  817. static int do_vdd_adjust(struct cmd_tbl *cmdtp,
  818. int flag, int argc,
  819. char *const argv[])
  820. {
  821. ulong override;
  822. if (argc < 2)
  823. return CMD_RET_USAGE;
  824. if (!strict_strtoul(argv[1], 10, &override))
  825. adjust_vdd(override); /* the value is checked by callee */
  826. else
  827. return CMD_RET_USAGE;
  828. return 0;
  829. }
  830. U_BOOT_CMD(
  831. vdd_override, 2, 0, do_vdd_adjust,
  832. "Override VDD",
  833. "- override with the voltage specified in mV, eg. 1050"
  834. );