t1040qds.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <env.h>
  9. #include <fdt_support.h>
  10. #include <i2c.h>
  11. #include <image.h>
  12. #include <init.h>
  13. #include <netdev.h>
  14. #include <linux/compiler.h>
  15. #include <asm/mmu.h>
  16. #include <asm/processor.h>
  17. #include <asm/cache.h>
  18. #include <asm/immap_85xx.h>
  19. #include <asm/fsl_law.h>
  20. #include <asm/fsl_serdes.h>
  21. #include <asm/fsl_liodn.h>
  22. #include <fm_eth.h>
  23. #include <hwconfig.h>
  24. #include "../common/sleep.h"
  25. #include "../common/qixis.h"
  26. #include "t1040qds.h"
  27. #include "t1040qds_qixis.h"
  28. DECLARE_GLOBAL_DATA_PTR;
  29. int checkboard(void)
  30. {
  31. char buf[64];
  32. u8 sw;
  33. struct cpu_type *cpu = gd->arch.cpu;
  34. static const char *const freq[] = {"100", "125", "156.25", "161.13",
  35. "122.88", "122.88", "122.88"};
  36. int clock;
  37. printf("Board: %sQDS, ", cpu->name);
  38. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
  39. QIXIS_READ(id), QIXIS_READ(arch));
  40. sw = QIXIS_READ(brdcfg[0]);
  41. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  42. if (sw < 0x8)
  43. printf("vBank: %d\n", sw);
  44. else if (sw == 0x8)
  45. puts("PromJet\n");
  46. else if (sw == 0x9)
  47. puts("NAND\n");
  48. else if (sw == 0x15)
  49. printf("IFCCard\n");
  50. else
  51. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  52. printf("FPGA: v%d (%s), build %d",
  53. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  54. (int)qixis_read_minor());
  55. /* the timestamp string contains "\n" at the end */
  56. printf(" on %s", qixis_read_time(buf));
  57. /*
  58. * Display the actual SERDES reference clocks as configured by the
  59. * dip switches on the board. Note that the SWx registers could
  60. * technically be set to force the reference clocks to match the
  61. * values that the SERDES expects (or vice versa). For now, however,
  62. * we just display both values and hope the user notices when they
  63. * don't match.
  64. */
  65. puts("SERDES Reference: ");
  66. sw = QIXIS_READ(brdcfg[2]);
  67. clock = (sw >> 6) & 3;
  68. printf("Clock1=%sMHz ", freq[clock]);
  69. clock = (sw >> 4) & 3;
  70. printf("Clock2=%sMHz\n", freq[clock]);
  71. return 0;
  72. }
  73. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  74. {
  75. int ret;
  76. #ifdef CONFIG_DM_I2C
  77. struct udevice *dev;
  78. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  79. if (ret) {
  80. printf("%s: Cannot find udev for a bus %d\n", __func__,
  81. bus_num);
  82. return ret;
  83. }
  84. ret = dm_i2c_write(dev, 0, &ch, 1);
  85. #else
  86. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  87. #endif
  88. if (ret) {
  89. puts("PCA: failed to select proper channel\n");
  90. return ret;
  91. }
  92. return 0;
  93. }
  94. static void qe_board_setup(void)
  95. {
  96. u8 brdcfg15, brdcfg9;
  97. if (hwconfig("qe") && hwconfig("tdm")) {
  98. brdcfg15 = QIXIS_READ(brdcfg[15]);
  99. /*
  100. * TDMRiser uses QE-TDM
  101. * Route QE_TDM signals to TDM Riser slot
  102. */
  103. QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
  104. } else if (hwconfig("qe") && hwconfig("uart")) {
  105. brdcfg15 = QIXIS_READ(brdcfg[15]);
  106. brdcfg9 = QIXIS_READ(brdcfg[9]);
  107. /*
  108. * Route QE_TDM signals to UCC
  109. * ProfiBus controlled by UCC3
  110. */
  111. brdcfg15 &= 0xfc;
  112. QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
  113. QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
  114. }
  115. }
  116. int board_early_init_f(void)
  117. {
  118. #if defined(CONFIG_DEEP_SLEEP)
  119. if (is_warm_boot())
  120. fsl_dp_disable_console();
  121. #endif
  122. return 0;
  123. }
  124. int board_early_init_r(void)
  125. {
  126. #ifdef CONFIG_SYS_FLASH_BASE
  127. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  128. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  129. /*
  130. * Remap Boot flash + PROMJET region to caching-inhibited
  131. * so that flash can be erased properly.
  132. */
  133. /* Flush d-cache and invalidate i-cache of any FLASH data */
  134. flush_dcache();
  135. invalidate_icache();
  136. if (flash_esel == -1) {
  137. /* very unlikely unless something is messed up */
  138. puts("Error: Could not find TLB for FLASH BASE\n");
  139. flash_esel = 2; /* give our best effort to continue */
  140. } else {
  141. /* invalidate existing TLB entry for flash + promjet */
  142. disable_tlb(flash_esel);
  143. }
  144. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  145. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  146. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  147. #endif
  148. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  149. return 0;
  150. }
  151. unsigned long get_board_sys_clk(void)
  152. {
  153. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  154. switch (sysclk_conf & 0x0F) {
  155. case QIXIS_SYSCLK_64:
  156. return 64000000;
  157. case QIXIS_SYSCLK_83:
  158. return 83333333;
  159. case QIXIS_SYSCLK_100:
  160. return 100000000;
  161. case QIXIS_SYSCLK_125:
  162. return 125000000;
  163. case QIXIS_SYSCLK_133:
  164. return 133333333;
  165. case QIXIS_SYSCLK_150:
  166. return 150000000;
  167. case QIXIS_SYSCLK_160:
  168. return 160000000;
  169. case QIXIS_SYSCLK_166:
  170. return 166666666;
  171. }
  172. return 66666666;
  173. }
  174. unsigned long get_board_ddr_clk(void)
  175. {
  176. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  177. switch ((ddrclk_conf & 0x30) >> 4) {
  178. case QIXIS_DDRCLK_100:
  179. return 100000000;
  180. case QIXIS_DDRCLK_125:
  181. return 125000000;
  182. case QIXIS_DDRCLK_133:
  183. return 133333333;
  184. }
  185. return 66666666;
  186. }
  187. #define NUM_SRDS_BANKS 2
  188. int misc_init_r(void)
  189. {
  190. u8 sw;
  191. serdes_corenet_t *srds_regs =
  192. (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  193. u32 actual[NUM_SRDS_BANKS] = { 0 };
  194. int i;
  195. sw = QIXIS_READ(brdcfg[2]);
  196. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  197. unsigned int clock = (sw >> (6 - 2 * i)) & 3;
  198. switch (clock) {
  199. case 0:
  200. actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
  201. break;
  202. case 1:
  203. actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
  204. break;
  205. case 2:
  206. actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
  207. break;
  208. }
  209. }
  210. puts("SerDes1");
  211. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  212. u32 pllcr0 = srds_regs->bank[i].pllcr0;
  213. u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
  214. if (expected != actual[i]) {
  215. printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
  216. i + 1, serdes_clock_to_string(expected),
  217. serdes_clock_to_string(actual[i]));
  218. }
  219. }
  220. qe_board_setup();
  221. return 0;
  222. }
  223. int ft_board_setup(void *blob, bd_t *bd)
  224. {
  225. phys_addr_t base;
  226. phys_size_t size;
  227. ft_cpu_setup(blob, bd);
  228. base = env_get_bootm_low();
  229. size = env_get_bootm_size();
  230. fdt_fixup_memory(blob, (u64)base, (u64)size);
  231. #ifdef CONFIG_PCI
  232. pci_of_setup(blob, bd);
  233. #endif
  234. fdt_fixup_liodn(blob);
  235. #ifdef CONFIG_HAS_FSL_DR_USB
  236. fsl_fdt_fixup_dr_usb(blob, bd);
  237. #endif
  238. #ifdef CONFIG_SYS_DPAA_FMAN
  239. #ifndef CONFIG_DM_ETH
  240. fdt_fixup_fman_ethernet(blob);
  241. #endif
  242. fdt_fixup_board_enet(blob);
  243. #endif
  244. return 0;
  245. }
  246. void qixis_dump_switch(void)
  247. {
  248. int i, nr_of_cfgsw;
  249. QIXIS_WRITE(cms[0], 0x00);
  250. nr_of_cfgsw = QIXIS_READ(cms[1]);
  251. puts("DIP switch settings dump:\n");
  252. for (i = 1; i <= nr_of_cfgsw; i++) {
  253. QIXIS_WRITE(cms[0], i);
  254. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  255. }
  256. }
  257. int board_need_mem_reset(void)
  258. {
  259. return 1;
  260. }