t102xqds.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <env.h>
  9. #include <fdt_support.h>
  10. #include <i2c.h>
  11. #include <image.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <netdev.h>
  15. #include <linux/compiler.h>
  16. #include <asm/mmu.h>
  17. #include <asm/processor.h>
  18. #include <asm/cache.h>
  19. #include <asm/immap_85xx.h>
  20. #include <asm/fsl_law.h>
  21. #include <asm/fsl_serdes.h>
  22. #include <asm/fsl_liodn.h>
  23. #include <fm_eth.h>
  24. #include <hwconfig.h>
  25. #include "../common/qixis.h"
  26. #include "t102xqds.h"
  27. #include "t102xqds_qixis.h"
  28. #include "../common/sleep.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. int checkboard(void)
  31. {
  32. char buf[64];
  33. struct cpu_type *cpu = gd->arch.cpu;
  34. static const char *const freq[] = {"100", "125", "156.25", "100.0"};
  35. int clock;
  36. u8 sw = QIXIS_READ(arch);
  37. printf("Board: %sQDS, ", cpu->name);
  38. printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  39. printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  40. #ifdef CONFIG_SDCARD
  41. puts("SD/MMC\n");
  42. #elif CONFIG_SPIFLASH
  43. puts("SPI\n");
  44. #else
  45. sw = QIXIS_READ(brdcfg[0]);
  46. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  47. if (sw < 0x8)
  48. printf("vBank: %d\n", sw);
  49. else if (sw == 0x8)
  50. puts("PromJet\n");
  51. else if (sw == 0x9)
  52. puts("NAND\n");
  53. else if (sw == 0x15)
  54. printf("IFC Card\n");
  55. else
  56. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  57. #endif
  58. printf("FPGA: v%d (%s), build %d",
  59. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  60. (int)qixis_read_minor());
  61. /* the timestamp string contains "\n" at the end */
  62. printf(" on %s", qixis_read_time(buf));
  63. puts("SERDES Reference: ");
  64. sw = QIXIS_READ(brdcfg[2]);
  65. clock = (sw >> 6) & 3;
  66. printf("Clock1=%sMHz ", freq[clock]);
  67. clock = (sw >> 4) & 3;
  68. printf("Clock2=%sMHz\n", freq[clock]);
  69. return 0;
  70. }
  71. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  72. {
  73. int ret;
  74. #ifdef CONFIG_DM_I2C
  75. struct udevice *dev;
  76. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  77. 1, &dev);
  78. if (ret) {
  79. printf("%s: Cannot find udev for a bus %d\n", __func__,
  80. bus_num);
  81. return ret;
  82. }
  83. ret = dm_i2c_write(dev, 0, &ch, 1);
  84. #else
  85. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  86. #endif
  87. if (ret) {
  88. puts("PCA: failed to select proper channel\n");
  89. return ret;
  90. }
  91. return 0;
  92. }
  93. static int board_mux_lane_to_slot(void)
  94. {
  95. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  96. u32 srds_prtcl_s1;
  97. u8 brdcfg9;
  98. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  99. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  100. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  101. brdcfg9 = QIXIS_READ(brdcfg[9]);
  102. QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
  103. switch (srds_prtcl_s1) {
  104. case 0:
  105. /* SerDes1 is not enabled */
  106. break;
  107. case 0xd5:
  108. case 0x5b:
  109. case 0x6b:
  110. case 0x77:
  111. case 0x6f:
  112. case 0x7f:
  113. QIXIS_WRITE(brdcfg[12], 0x8c);
  114. break;
  115. case 0x40:
  116. QIXIS_WRITE(brdcfg[12], 0xfc);
  117. break;
  118. case 0xd6:
  119. case 0x5a:
  120. case 0x6a:
  121. case 0x56:
  122. QIXIS_WRITE(brdcfg[12], 0x88);
  123. break;
  124. case 0x47:
  125. QIXIS_WRITE(brdcfg[12], 0xcc);
  126. break;
  127. case 0x46:
  128. QIXIS_WRITE(brdcfg[12], 0xc8);
  129. break;
  130. case 0x95:
  131. case 0x99:
  132. brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
  133. QIXIS_WRITE(brdcfg[9], brdcfg9);
  134. QIXIS_WRITE(brdcfg[12], 0x8c);
  135. break;
  136. case 0x116:
  137. QIXIS_WRITE(brdcfg[12], 0x00);
  138. break;
  139. case 0x115:
  140. case 0x119:
  141. case 0x129:
  142. case 0x12b:
  143. /* Aurora, PCIe, SGMII, SATA */
  144. QIXIS_WRITE(brdcfg[12], 0x04);
  145. break;
  146. default:
  147. printf("WARNING: unsupported for SerDes Protocol %d\n",
  148. srds_prtcl_s1);
  149. return -1;
  150. }
  151. return 0;
  152. }
  153. #ifdef CONFIG_ARCH_T1024
  154. static void board_mux_setup(void)
  155. {
  156. u8 brdcfg15;
  157. brdcfg15 = QIXIS_READ(brdcfg[15]);
  158. brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
  159. if (hwconfig_arg_cmp("pin_mux", "tdm")) {
  160. /* Route QE_TDM multiplexed signals to TDM Riser slot */
  161. QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
  162. QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
  163. QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
  164. ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
  165. } else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
  166. /* to UCC (ProfiBus) interface */
  167. QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
  168. } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
  169. /* to DVI (HDMI) encoder */
  170. QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
  171. } else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
  172. /* to DFP (LCD) encoder */
  173. QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
  174. BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
  175. }
  176. if (hwconfig_arg_cmp("adaptor", "sdxc"))
  177. /* Route SPI_CS multiplexed signals to SD slot */
  178. QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
  179. ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
  180. }
  181. #endif
  182. void board_retimer_ds125df111_init(void)
  183. {
  184. u8 reg;
  185. #ifdef CONFIG_DM_I2C
  186. struct udevice *dev;
  187. int ret, bus_num = 0;
  188. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  189. 1, &dev);
  190. if (ret)
  191. goto failed;
  192. /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
  193. reg = I2C_MUX_CH7;
  194. dm_i2c_write(dev, 0, &reg, 1);
  195. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
  196. 1, &dev);
  197. if (ret)
  198. goto failed;
  199. reg = I2C_MUX_CH5;
  200. dm_i2c_write(dev, 0, &reg, 1);
  201. /* Access to Control/Shared register */
  202. ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
  203. 1, &dev);
  204. if (ret)
  205. goto failed;
  206. reg = 0x0;
  207. dm_i2c_write(dev, 0xff, &reg, 1);
  208. /* Read device revision and ID */
  209. dm_i2c_read(dev, 1, &reg, 1);
  210. debug("Retimer version id = 0x%x\n", reg);
  211. /* Enable Broadcast */
  212. reg = 0x0c;
  213. dm_i2c_write(dev, 0xff, &reg, 1);
  214. /* Reset Channel Registers */
  215. dm_i2c_read(dev, 0, &reg, 1);
  216. reg |= 0x4;
  217. dm_i2c_write(dev, 0, &reg, 1);
  218. /* Enable override divider select and Enable Override Output Mux */
  219. dm_i2c_read(dev, 9, &reg, 1);
  220. reg |= 0x24;
  221. dm_i2c_write(dev, 9, &reg, 1);
  222. /* Select VCO Divider to full rate (000) */
  223. dm_i2c_read(dev, 0x18, &reg, 1);
  224. reg &= 0x8f;
  225. dm_i2c_write(dev, 0x18, &reg, 1);
  226. /* Select active PFD MUX input as re-timed data (001) */
  227. dm_i2c_read(dev, 0x1e, &reg, 1);
  228. reg &= 0x3f;
  229. reg |= 0x20;
  230. dm_i2c_write(dev, 0x1e, &reg, 1);
  231. /* Set data rate as 10.3125 Gbps */
  232. reg = 0x0;
  233. dm_i2c_write(dev, 0x60, &reg, 1);
  234. reg = 0xb2;
  235. dm_i2c_write(dev, 0x61, &reg, 1);
  236. reg = 0x90;
  237. dm_i2c_write(dev, 0x62, &reg, 1);
  238. reg = 0xb3;
  239. dm_i2c_write(dev, 0x63, &reg, 1);
  240. reg = 0xcd;
  241. dm_i2c_write(dev, 0x64, &reg, 1);
  242. return;
  243. failed:
  244. printf("%s: Cannot find udev for a bus %d\n", __func__,
  245. bus_num);
  246. return;
  247. #else
  248. /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
  249. reg = I2C_MUX_CH7;
  250. i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
  251. reg = I2C_MUX_CH5;
  252. i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
  253. /* Access to Control/Shared register */
  254. reg = 0x0;
  255. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  256. /* Read device revision and ID */
  257. i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
  258. debug("Retimer version id = 0x%x\n", reg);
  259. /* Enable Broadcast */
  260. reg = 0x0c;
  261. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  262. /* Reset Channel Registers */
  263. i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  264. reg |= 0x4;
  265. i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  266. /* Enable override divider select and Enable Override Output Mux */
  267. i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  268. reg |= 0x24;
  269. i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  270. /* Select VCO Divider to full rate (000) */
  271. i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  272. reg &= 0x8f;
  273. i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  274. /* Select active PFD MUX input as re-timed data (001) */
  275. i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  276. reg &= 0x3f;
  277. reg |= 0x20;
  278. i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  279. /* Set data rate as 10.3125 Gbps */
  280. reg = 0x0;
  281. i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
  282. reg = 0xb2;
  283. i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
  284. reg = 0x90;
  285. i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
  286. reg = 0xb3;
  287. i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
  288. reg = 0xcd;
  289. i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
  290. #endif
  291. }
  292. int board_early_init_f(void)
  293. {
  294. #if defined(CONFIG_DEEP_SLEEP)
  295. if (is_warm_boot())
  296. fsl_dp_disable_console();
  297. #endif
  298. return 0;
  299. }
  300. int board_early_init_r(void)
  301. {
  302. #ifdef CONFIG_SYS_FLASH_BASE
  303. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  304. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  305. /*
  306. * Remap Boot flash + PROMJET region to caching-inhibited
  307. * so that flash can be erased properly.
  308. */
  309. /* Flush d-cache and invalidate i-cache of any FLASH data */
  310. flush_dcache();
  311. invalidate_icache();
  312. if (flash_esel == -1) {
  313. /* very unlikely unless something is messed up */
  314. puts("Error: Could not find TLB for FLASH BASE\n");
  315. flash_esel = 2; /* give our best effort to continue */
  316. } else {
  317. /* invalidate existing TLB entry for flash + promjet */
  318. disable_tlb(flash_esel);
  319. }
  320. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  321. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  322. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  323. #endif
  324. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  325. board_mux_lane_to_slot();
  326. board_retimer_ds125df111_init();
  327. /* Increase IO drive strength to address FCS error on RGMII */
  328. out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
  329. return 0;
  330. }
  331. unsigned long get_board_sys_clk(void)
  332. {
  333. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  334. switch (sysclk_conf & 0x0F) {
  335. case QIXIS_SYSCLK_64:
  336. return 64000000;
  337. case QIXIS_SYSCLK_83:
  338. return 83333333;
  339. case QIXIS_SYSCLK_100:
  340. return 100000000;
  341. case QIXIS_SYSCLK_125:
  342. return 125000000;
  343. case QIXIS_SYSCLK_133:
  344. return 133333333;
  345. case QIXIS_SYSCLK_150:
  346. return 150000000;
  347. case QIXIS_SYSCLK_160:
  348. return 160000000;
  349. case QIXIS_SYSCLK_166:
  350. return 166666666;
  351. }
  352. return 66666666;
  353. }
  354. unsigned long get_board_ddr_clk(void)
  355. {
  356. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  357. switch ((ddrclk_conf & 0x30) >> 4) {
  358. case QIXIS_DDRCLK_100:
  359. return 100000000;
  360. case QIXIS_DDRCLK_125:
  361. return 125000000;
  362. case QIXIS_DDRCLK_133:
  363. return 133333333;
  364. }
  365. return 66666666;
  366. }
  367. #define NUM_SRDS_PLL 2
  368. int misc_init_r(void)
  369. {
  370. #ifdef CONFIG_ARCH_T1024
  371. board_mux_setup();
  372. #endif
  373. return 0;
  374. }
  375. void fdt_fixup_spi_mux(void *blob)
  376. {
  377. int nodeoff = 0;
  378. if (hwconfig_arg_cmp("pin_mux", "tdm")) {
  379. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  380. "eon,en25s64")) >= 0) {
  381. fdt_del_node(blob, nodeoff);
  382. }
  383. } else {
  384. /* remove tdm node */
  385. while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
  386. "maxim,ds26522")) >= 0) {
  387. fdt_del_node(blob, nodeoff);
  388. }
  389. }
  390. }
  391. int ft_board_setup(void *blob, bd_t *bd)
  392. {
  393. phys_addr_t base;
  394. phys_size_t size;
  395. ft_cpu_setup(blob, bd);
  396. base = env_get_bootm_low();
  397. size = env_get_bootm_size();
  398. fdt_fixup_memory(blob, (u64)base, (u64)size);
  399. #ifdef CONFIG_PCI
  400. pci_of_setup(blob, bd);
  401. #endif
  402. fdt_fixup_liodn(blob);
  403. #ifdef CONFIG_HAS_FSL_DR_USB
  404. fsl_fdt_fixup_dr_usb(blob, bd);
  405. #endif
  406. #ifdef CONFIG_SYS_DPAA_FMAN
  407. #ifndef CONFIG_DM_ETH
  408. fdt_fixup_fman_ethernet(blob);
  409. #endif
  410. fdt_fixup_board_enet(blob);
  411. #endif
  412. fdt_fixup_spi_mux(blob);
  413. return 0;
  414. }
  415. void qixis_dump_switch(void)
  416. {
  417. int i, nr_of_cfgsw;
  418. QIXIS_WRITE(cms[0], 0x00);
  419. nr_of_cfgsw = QIXIS_READ(cms[1]);
  420. puts("DIP switch settings dump:\n");
  421. for (i = 1; i <= nr_of_cfgsw; i++) {
  422. QIXIS_WRITE(cms[0], i);
  423. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  424. }
  425. }