ls1043aqds.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #include <common.h>
  7. #include <i2c.h>
  8. #include <fdt_support.h>
  9. #include <fsl_ddr_sdram.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/fsl_serdes.h>
  15. #include <asm/arch/ppa.h>
  16. #include <asm/arch/fdt.h>
  17. #include <asm/arch/mmu.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/soc.h>
  20. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  21. #include <ahci.h>
  22. #include <hwconfig.h>
  23. #include <mmc.h>
  24. #include <scsi.h>
  25. #include <fm_eth.h>
  26. #include <fsl_esdhc.h>
  27. #include <fsl_ifc.h>
  28. #include <spl.h>
  29. #include "../common/qixis.h"
  30. #include "ls1043aqds_qixis.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. enum {
  33. MUX_TYPE_GPIO,
  34. };
  35. /* LS1043AQDS serdes mux */
  36. #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
  37. #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
  38. #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
  39. #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
  40. #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
  41. #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
  42. #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
  43. #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
  44. #define CFG_UART_MUX_MASK 0x6
  45. #define CFG_UART_MUX_SHIFT 1
  46. #define CFG_LPUART_EN 0x1
  47. #ifdef CONFIG_TFABOOT
  48. struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  49. {
  50. "nor0",
  51. CONFIG_SYS_NOR0_CSPR,
  52. CONFIG_SYS_NOR0_CSPR_EXT,
  53. CONFIG_SYS_NOR_AMASK,
  54. CONFIG_SYS_NOR_CSOR,
  55. {
  56. CONFIG_SYS_NOR_FTIM0,
  57. CONFIG_SYS_NOR_FTIM1,
  58. CONFIG_SYS_NOR_FTIM2,
  59. CONFIG_SYS_NOR_FTIM3
  60. },
  61. },
  62. {
  63. "nor1",
  64. CONFIG_SYS_NOR1_CSPR,
  65. CONFIG_SYS_NOR1_CSPR_EXT,
  66. CONFIG_SYS_NOR_AMASK,
  67. CONFIG_SYS_NOR_CSOR,
  68. {
  69. CONFIG_SYS_NOR_FTIM0,
  70. CONFIG_SYS_NOR_FTIM1,
  71. CONFIG_SYS_NOR_FTIM2,
  72. CONFIG_SYS_NOR_FTIM3
  73. },
  74. },
  75. {
  76. "nand",
  77. CONFIG_SYS_NAND_CSPR,
  78. CONFIG_SYS_NAND_CSPR_EXT,
  79. CONFIG_SYS_NAND_AMASK,
  80. CONFIG_SYS_NAND_CSOR,
  81. {
  82. CONFIG_SYS_NAND_FTIM0,
  83. CONFIG_SYS_NAND_FTIM1,
  84. CONFIG_SYS_NAND_FTIM2,
  85. CONFIG_SYS_NAND_FTIM3
  86. },
  87. },
  88. {
  89. "fpga",
  90. CONFIG_SYS_FPGA_CSPR,
  91. CONFIG_SYS_FPGA_CSPR_EXT,
  92. CONFIG_SYS_FPGA_AMASK,
  93. CONFIG_SYS_FPGA_CSOR,
  94. {
  95. CONFIG_SYS_FPGA_FTIM0,
  96. CONFIG_SYS_FPGA_FTIM1,
  97. CONFIG_SYS_FPGA_FTIM2,
  98. CONFIG_SYS_FPGA_FTIM3
  99. },
  100. }
  101. };
  102. struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
  103. {
  104. "nand",
  105. CONFIG_SYS_NAND_CSPR,
  106. CONFIG_SYS_NAND_CSPR_EXT,
  107. CONFIG_SYS_NAND_AMASK,
  108. CONFIG_SYS_NAND_CSOR,
  109. {
  110. CONFIG_SYS_NAND_FTIM0,
  111. CONFIG_SYS_NAND_FTIM1,
  112. CONFIG_SYS_NAND_FTIM2,
  113. CONFIG_SYS_NAND_FTIM3
  114. },
  115. },
  116. {
  117. "nor0",
  118. CONFIG_SYS_NOR0_CSPR,
  119. CONFIG_SYS_NOR0_CSPR_EXT,
  120. CONFIG_SYS_NOR_AMASK,
  121. CONFIG_SYS_NOR_CSOR,
  122. {
  123. CONFIG_SYS_NOR_FTIM0,
  124. CONFIG_SYS_NOR_FTIM1,
  125. CONFIG_SYS_NOR_FTIM2,
  126. CONFIG_SYS_NOR_FTIM3
  127. },
  128. },
  129. {
  130. "nor1",
  131. CONFIG_SYS_NOR1_CSPR,
  132. CONFIG_SYS_NOR1_CSPR_EXT,
  133. CONFIG_SYS_NOR_AMASK,
  134. CONFIG_SYS_NOR_CSOR,
  135. {
  136. CONFIG_SYS_NOR_FTIM0,
  137. CONFIG_SYS_NOR_FTIM1,
  138. CONFIG_SYS_NOR_FTIM2,
  139. CONFIG_SYS_NOR_FTIM3
  140. },
  141. },
  142. {
  143. "fpga",
  144. CONFIG_SYS_FPGA_CSPR,
  145. CONFIG_SYS_FPGA_CSPR_EXT,
  146. CONFIG_SYS_FPGA_AMASK,
  147. CONFIG_SYS_FPGA_CSOR,
  148. {
  149. CONFIG_SYS_FPGA_FTIM0,
  150. CONFIG_SYS_FPGA_FTIM1,
  151. CONFIG_SYS_FPGA_FTIM2,
  152. CONFIG_SYS_FPGA_FTIM3
  153. },
  154. }
  155. };
  156. void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
  157. {
  158. enum boot_src src = get_boot_src();
  159. if (src == BOOT_SOURCE_IFC_NAND)
  160. regs_info->regs = ifc_cfg_nand_boot;
  161. else
  162. regs_info->regs = ifc_cfg_nor_boot;
  163. regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
  164. }
  165. #endif
  166. int checkboard(void)
  167. {
  168. #ifdef CONFIG_TFABOOT
  169. enum boot_src src = get_boot_src();
  170. #endif
  171. char buf[64];
  172. #ifndef CONFIG_SD_BOOT
  173. u8 sw;
  174. #endif
  175. puts("Board: LS1043AQDS, boot from ");
  176. #ifdef CONFIG_TFABOOT
  177. if (src == BOOT_SOURCE_SD_MMC)
  178. puts("SD\n");
  179. else {
  180. #endif
  181. #ifdef CONFIG_SD_BOOT
  182. puts("SD\n");
  183. #else
  184. sw = QIXIS_READ(brdcfg[0]);
  185. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  186. if (sw < 0x8)
  187. printf("vBank: %d\n", sw);
  188. else if (sw == 0x8)
  189. puts("PromJet\n");
  190. else if (sw == 0x9)
  191. puts("NAND\n");
  192. else if (sw == 0xF)
  193. printf("QSPI\n");
  194. else
  195. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  196. #endif
  197. #ifdef CONFIG_TFABOOT
  198. }
  199. #endif
  200. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
  201. QIXIS_READ(id), QIXIS_READ(arch));
  202. printf("FPGA: v%d (%s), build %d\n",
  203. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  204. (int)qixis_read_minor());
  205. return 0;
  206. }
  207. bool if_board_diff_clk(void)
  208. {
  209. u8 diff_conf = QIXIS_READ(brdcfg[11]);
  210. return diff_conf & 0x40;
  211. }
  212. unsigned long get_board_sys_clk(void)
  213. {
  214. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  215. switch (sysclk_conf & 0x0f) {
  216. case QIXIS_SYSCLK_64:
  217. return 64000000;
  218. case QIXIS_SYSCLK_83:
  219. return 83333333;
  220. case QIXIS_SYSCLK_100:
  221. return 100000000;
  222. case QIXIS_SYSCLK_125:
  223. return 125000000;
  224. case QIXIS_SYSCLK_133:
  225. return 133333333;
  226. case QIXIS_SYSCLK_150:
  227. return 150000000;
  228. case QIXIS_SYSCLK_160:
  229. return 160000000;
  230. case QIXIS_SYSCLK_166:
  231. return 166666666;
  232. }
  233. return 66666666;
  234. }
  235. unsigned long get_board_ddr_clk(void)
  236. {
  237. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  238. if (if_board_diff_clk())
  239. return get_board_sys_clk();
  240. switch ((ddrclk_conf & 0x30) >> 4) {
  241. case QIXIS_DDRCLK_100:
  242. return 100000000;
  243. case QIXIS_DDRCLK_125:
  244. return 125000000;
  245. case QIXIS_DDRCLK_133:
  246. return 133333333;
  247. }
  248. return 66666666;
  249. }
  250. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  251. {
  252. int ret;
  253. #ifdef CONFIG_DM_I2C
  254. struct udevice *dev;
  255. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
  256. 1, &dev);
  257. if (ret) {
  258. printf("%s: Cannot find udev for a bus %d\n", __func__,
  259. bus_num);
  260. return ret;
  261. }
  262. ret = dm_i2c_write(dev, 0, &ch, 1);
  263. #else
  264. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  265. #endif
  266. if (ret) {
  267. puts("PCA: failed to select proper channel\n");
  268. return ret;
  269. }
  270. return 0;
  271. }
  272. int dram_init(void)
  273. {
  274. /*
  275. * When resuming from deep sleep, the I2C channel may not be
  276. * in the default channel. So, switch to the default channel
  277. * before accessing DDR SPD.
  278. *
  279. * PCA9547 mount on I2C1 bus
  280. */
  281. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  282. fsl_initdram();
  283. #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
  284. defined(CONFIG_SPL_BUILD)
  285. /* This will break-before-make MMU for DDR */
  286. update_early_mmu_table();
  287. #endif
  288. return 0;
  289. }
  290. int i2c_multiplexer_select_vid_channel(u8 channel)
  291. {
  292. return select_i2c_ch_pca9547(channel, 0);
  293. }
  294. void board_retimer_init(void)
  295. {
  296. u8 reg;
  297. int bus_num = 0;
  298. /* Retimer is connected to I2C1_CH7_CH5 */
  299. select_i2c_ch_pca9547(I2C_MUX_CH7, bus_num);
  300. reg = I2C_MUX_CH5;
  301. #ifdef CONFIG_DM_I2C
  302. struct udevice *dev;
  303. int ret;
  304. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
  305. 1, &dev);
  306. if (ret) {
  307. printf("%s: Cannot find udev for a bus %d\n", __func__,
  308. bus_num);
  309. return;
  310. }
  311. dm_i2c_write(dev, 0, &reg, 1);
  312. /* Access to Control/Shared register */
  313. ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
  314. 1, &dev);
  315. if (ret) {
  316. printf("%s: Cannot find udev for a bus %d\n", __func__,
  317. bus_num);
  318. return;
  319. }
  320. reg = 0x0;
  321. dm_i2c_write(dev, 0xff, &reg, 1);
  322. /* Read device revision and ID */
  323. dm_i2c_read(dev, 1, &reg, 1);
  324. debug("Retimer version id = 0x%x\n", reg);
  325. /* Enable Broadcast. All writes target all channel register sets */
  326. reg = 0x0c;
  327. dm_i2c_write(dev, 0xff, &reg, 1);
  328. /* Reset Channel Registers */
  329. dm_i2c_read(dev, 0, &reg, 1);
  330. reg |= 0x4;
  331. dm_i2c_write(dev, 0, &reg, 1);
  332. /* Enable override divider select and Enable Override Output Mux */
  333. dm_i2c_read(dev, 9, &reg, 1);
  334. reg |= 0x24;
  335. dm_i2c_write(dev, 9, &reg, 1);
  336. /* Select VCO Divider to full rate (000) */
  337. dm_i2c_read(dev, 0x18, &reg, 1);
  338. reg &= 0x8f;
  339. dm_i2c_write(dev, 0x18, &reg, 1);
  340. /* Selects active PFD MUX Input as Re-timed Data (001) */
  341. dm_i2c_read(dev, 0x1e, &reg, 1);
  342. reg &= 0x3f;
  343. reg |= 0x20;
  344. dm_i2c_write(dev, 0x1e, &reg, 1);
  345. /* Set data rate as 10.3125 Gbps */
  346. reg = 0x0;
  347. dm_i2c_write(dev, 0x60, &reg, 1);
  348. reg = 0xb2;
  349. dm_i2c_write(dev, 0x61, &reg, 1);
  350. reg = 0x90;
  351. dm_i2c_write(dev, 0x62, &reg, 1);
  352. reg = 0xb3;
  353. dm_i2c_write(dev, 0x63, &reg, 1);
  354. reg = 0xcd;
  355. dm_i2c_write(dev, 0x64, &reg, 1);
  356. #else
  357. i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
  358. /* Access to Control/Shared register */
  359. reg = 0x0;
  360. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  361. /* Read device revision and ID */
  362. i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
  363. debug("Retimer version id = 0x%x\n", reg);
  364. /* Enable Broadcast. All writes target all channel register sets */
  365. reg = 0x0c;
  366. i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
  367. /* Reset Channel Registers */
  368. i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  369. reg |= 0x4;
  370. i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
  371. /* Enable override divider select and Enable Override Output Mux */
  372. i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  373. reg |= 0x24;
  374. i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
  375. /* Select VCO Divider to full rate (000) */
  376. i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  377. reg &= 0x8f;
  378. i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
  379. /* Selects active PFD MUX Input as Re-timed Data (001) */
  380. i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  381. reg &= 0x3f;
  382. reg |= 0x20;
  383. i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
  384. /* Set data rate as 10.3125 Gbps */
  385. reg = 0x0;
  386. i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
  387. reg = 0xb2;
  388. i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
  389. reg = 0x90;
  390. i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
  391. reg = 0xb3;
  392. i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
  393. reg = 0xcd;
  394. i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
  395. #endif
  396. /* Return the default channel */
  397. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, bus_num);
  398. }
  399. int board_early_init_f(void)
  400. {
  401. #ifdef CONFIG_HAS_FSL_XHCI_USB
  402. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  403. u32 usb_pwrfault;
  404. #endif
  405. #ifdef CONFIG_LPUART
  406. u8 uart;
  407. #endif
  408. #ifdef CONFIG_SYS_I2C
  409. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  410. i2c_early_init_f();
  411. #endif
  412. #endif
  413. fsl_lsch2_early_init_f();
  414. #ifdef CONFIG_HAS_FSL_XHCI_USB
  415. out_be32(&scfg->rcwpmuxcr0, 0x3333);
  416. out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
  417. usb_pwrfault =
  418. (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
  419. (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
  420. (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
  421. out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
  422. #endif
  423. #ifdef CONFIG_LPUART
  424. /* We use lpuart0 as system console */
  425. uart = QIXIS_READ(brdcfg[14]);
  426. uart &= ~CFG_UART_MUX_MASK;
  427. uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
  428. QIXIS_WRITE(brdcfg[14], uart);
  429. #endif
  430. return 0;
  431. }
  432. #ifdef CONFIG_FSL_DEEP_SLEEP
  433. /* determine if it is a warm boot */
  434. bool is_warm_boot(void)
  435. {
  436. #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
  437. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  438. if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
  439. return 1;
  440. return 0;
  441. }
  442. #endif
  443. int config_board_mux(int ctrl_type)
  444. {
  445. u8 reg14;
  446. reg14 = QIXIS_READ(brdcfg[14]);
  447. switch (ctrl_type) {
  448. case MUX_TYPE_GPIO:
  449. reg14 = (reg14 & (~0x30)) | 0x20;
  450. break;
  451. default:
  452. puts("Unsupported mux interface type\n");
  453. return -1;
  454. }
  455. QIXIS_WRITE(brdcfg[14], reg14);
  456. return 0;
  457. }
  458. int config_serdes_mux(void)
  459. {
  460. return 0;
  461. }
  462. #ifdef CONFIG_MISC_INIT_R
  463. int misc_init_r(void)
  464. {
  465. if (hwconfig("gpio"))
  466. config_board_mux(MUX_TYPE_GPIO);
  467. return 0;
  468. }
  469. #endif
  470. int board_init(void)
  471. {
  472. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  473. erratum_a010315();
  474. #endif
  475. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  476. board_retimer_init();
  477. #ifdef CONFIG_SYS_FSL_SERDES
  478. config_serdes_mux();
  479. #endif
  480. #ifdef CONFIG_FSL_LS_PPA
  481. ppa_init();
  482. #endif
  483. return 0;
  484. }
  485. #ifdef CONFIG_OF_BOARD_SETUP
  486. int ft_board_setup(void *blob, bd_t *bd)
  487. {
  488. u64 base[CONFIG_NR_DRAM_BANKS];
  489. u64 size[CONFIG_NR_DRAM_BANKS];
  490. u8 reg;
  491. /* fixup DT for the two DDR banks */
  492. base[0] = gd->bd->bi_dram[0].start;
  493. size[0] = gd->bd->bi_dram[0].size;
  494. base[1] = gd->bd->bi_dram[1].start;
  495. size[1] = gd->bd->bi_dram[1].size;
  496. fdt_fixup_memory_banks(blob, base, size, 2);
  497. ft_cpu_setup(blob, bd);
  498. #ifdef CONFIG_SYS_DPAA_FMAN
  499. #ifndef CONFIG_DM_ETH
  500. fdt_fixup_fman_ethernet(blob);
  501. #endif
  502. fdt_fixup_board_enet(blob);
  503. #endif
  504. fdt_fixup_icid(blob);
  505. reg = QIXIS_READ(brdcfg[0]);
  506. reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  507. /* Disable IFC if QSPI is enabled */
  508. if (reg == 0xF)
  509. do_fixup_by_compat(blob, "fsl,ifc",
  510. "status", "disabled", 8 + 1, 1);
  511. return 0;
  512. }
  513. #endif
  514. u8 flash_read8(void *addr)
  515. {
  516. return __raw_readb(addr + 1);
  517. }
  518. void flash_write16(u16 val, void *addr)
  519. {
  520. u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
  521. __raw_writew(shftval, addr);
  522. }
  523. u16 flash_read16(void *addr)
  524. {
  525. u16 val = __raw_readw(addr);
  526. return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
  527. }
  528. #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  529. void *env_sf_get_env_addr(void)
  530. {
  531. return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
  532. }
  533. #endif