p5040ds.dts 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P5040DS Device Tree Source
  4. *
  5. * Copyright 2012 - 2015 Freescale Semiconductor Inc.
  6. * Copyright 2019-2020 NXP
  7. */
  8. /include/ "p5040.dtsi"
  9. / {
  10. model = "fsl,P5040DS";
  11. compatible = "fsl,P5040DS";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. interrupt-parent = <&mpic>;
  15. aliases{
  16. phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
  17. phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
  18. phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
  19. phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
  20. phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
  21. phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
  22. phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
  23. phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
  24. phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
  25. phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
  26. phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
  27. phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
  28. phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
  29. phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
  30. phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
  31. phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
  32. hydra_rg = &hydra_rg;
  33. hydra_sg_slot2 = &hydra_sg_slot2;
  34. hydra_sg_slot3 = &hydra_sg_slot3;
  35. hydra_sg_slot5 = &hydra_sg_slot5;
  36. hydra_sg_slot6 = &hydra_sg_slot6;
  37. hydra_xg_slot1 = &hydra_xg_slot1;
  38. hydra_xg_slot2 = &hydra_xg_slot2;
  39. };
  40. soc: soc@ffe000000 {
  41. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  42. reg = <0xf 0xfe000000 0 0x00001000>;
  43. fman@400000 {
  44. ethernet@e0000 {
  45. phy-connection-type = "sgmii";
  46. };
  47. ethernet@e2000 {
  48. phy-connection-type = "sgmii";
  49. };
  50. ethernet@e4000 {
  51. phy-connection-type = "sgmii";
  52. };
  53. ethernet@e6000 {
  54. phy-connection-type = "sgmii";
  55. };
  56. ethernet@e8000 {
  57. phy-handle = <&phy_rgmii_0>;
  58. phy-connection-type = "rgmii";
  59. };
  60. ethernet@f0000 {
  61. phy-handle = <&phy_xgmii_slot_2>;
  62. phy-connection-type = "xgmii";
  63. };
  64. };
  65. fman@500000 {
  66. ethernet@e0000 {
  67. phy-connection-type = "sgmii";
  68. };
  69. ethernet@e2000 {
  70. phy-connection-type = "sgmii";
  71. };
  72. ethernet@e4000 {
  73. phy-connection-type = "sgmii";
  74. };
  75. ethernet@e6000 {
  76. phy-connection-type = "sgmii";
  77. };
  78. ethernet@e8000 {
  79. phy-handle = <&phy_rgmii_1>;
  80. phy-connection-type = "rgmii";
  81. };
  82. ethernet@f0000 {
  83. phy-handle = <&phy_xgmii_slot_1>;
  84. phy-connection-type = "xgmii";
  85. };
  86. };
  87. };
  88. lbc: localbus@ffe124000 {
  89. reg = <0xf 0xfe124000 0 0x1000>;
  90. ranges = <0 0 0xf 0xe8000000 0x08000000
  91. 2 0 0xf 0xffa00000 0x00040000
  92. 3 0 0xf 0xffdf0000 0x00008000>;
  93. board-control@3,0 {
  94. #address-cells = <1>;
  95. #size-cells = <1>;
  96. compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
  97. reg = <3 0 0x40>;
  98. ranges = <0 3 0 0x40>;
  99. mdio-mux-emi1 {
  100. #address-cells = <1>;
  101. #size-cells = <0>;
  102. compatible = "mdio-mux-mmioreg", "mdio-mux";
  103. mdio-parent-bus = <&mdio0>;
  104. reg = <9 1>;
  105. mux-mask = <0x78>;
  106. hydra_rg:rgmii-mdio@8 {
  107. #address-cells = <1>;
  108. #size-cells = <0>;
  109. reg = <8>;
  110. status = "disabled";
  111. phy_rgmii_0: ethernet-phy@0 {
  112. reg = <0x0>;
  113. };
  114. phy_rgmii_1: ethernet-phy@1 {
  115. reg = <0x1>;
  116. };
  117. };
  118. hydra_sg_slot2: sgmii-mdio@28 {
  119. #address-cells = <1>;
  120. #size-cells = <0>;
  121. reg = <0x28>;
  122. status = "disabled";
  123. phy_sgmii_slot2_1c: ethernet-phy@1c {
  124. reg = <0x1c>;
  125. };
  126. phy_sgmii_slot2_1d: ethernet-phy@1d {
  127. reg = <0x1d>;
  128. };
  129. phy_sgmii_slot2_1e: ethernet-phy@1e {
  130. reg = <0x1e>;
  131. };
  132. phy_sgmii_slot2_1f: ethernet-phy@1f {
  133. reg = <0x1f>;
  134. };
  135. };
  136. hydra_sg_slot3: sgmii-mdio@68 {
  137. #address-cells = <1>;
  138. #size-cells = <0>;
  139. reg = <0x68>;
  140. status = "disabled";
  141. phy_sgmii_slot3_1c: ethernet-phy@1c {
  142. reg = <0x1c>;
  143. };
  144. phy_sgmii_slot3_1d: ethernet-phy@1d {
  145. reg = <0x1d>;
  146. };
  147. phy_sgmii_slot3_1e: ethernet-phy@1e {
  148. reg = <0x1e>;
  149. };
  150. phy_sgmii_slot3_1f: ethernet-phy@1f {
  151. reg = <0x1f>;
  152. };
  153. };
  154. hydra_sg_slot5: sgmii-mdio@38 {
  155. #address-cells = <1>;
  156. #size-cells = <0>;
  157. reg = <0x38>;
  158. status = "disabled";
  159. phy_sgmii_slot5_1c: ethernet-phy@1c {
  160. reg = <0x1c>;
  161. };
  162. phy_sgmii_slot5_1d: ethernet-phy@1d {
  163. reg = <0x1d>;
  164. };
  165. phy_sgmii_slot5_1e: ethernet-phy@1e {
  166. reg = <0x1e>;
  167. };
  168. phy_sgmii_slot5_1f: ethernet-phy@1f {
  169. reg = <0x1f>;
  170. };
  171. };
  172. hydra_sg_slot6: sgmii-mdio@48 {
  173. #address-cells = <1>;
  174. #size-cells = <0>;
  175. reg = <0x48>;
  176. status = "disabled";
  177. phy_sgmii_slot6_1c: ethernet-phy@1c {
  178. reg = <0x1c>;
  179. };
  180. phy_sgmii_slot6_1d: ethernet-phy@1d {
  181. reg = <0x1d>;
  182. };
  183. phy_sgmii_slot6_1e: ethernet-phy@1e {
  184. reg = <0x1e>;
  185. };
  186. phy_sgmii_slot6_1f: ethernet-phy@1f {
  187. reg = <0x1f>;
  188. };
  189. };
  190. };
  191. mdio-mux-emi2 {
  192. #address-cells = <1>;
  193. #size-cells = <0>;
  194. compatible = "mdio-mux-mmioreg", "mdio-mux";
  195. mdio-parent-bus = <&xmdio0>;
  196. reg = <9 1>;
  197. mux-mask = <0x06>;
  198. hydra_xg_slot1: hydra-xg-slot1@0 {
  199. #address-cells = <1>;
  200. #size-cells = <0>;
  201. reg = <0>;
  202. status = "disabled";
  203. phy_xgmii_slot_1: ethernet-phy@0 {
  204. compatible = "ethernet-phy-ieee802.3-c45";
  205. reg = <4>;
  206. };
  207. };
  208. hydra_xg_slot2: hydra-xg-slot2@2 {
  209. #address-cells = <1>;
  210. #size-cells = <0>;
  211. reg = <2>;
  212. phy_xgmii_slot_2: ethernet-phy@4 {
  213. compatible = "ethernet-phy-ieee802.3-c45";
  214. reg = <0>;
  215. };
  216. };
  217. };
  218. };
  219. };
  220. };
  221. /include/ "p5040si-post.dtsi"