p4080ds.dts 3.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P4080DS Device Tree Source
  4. *
  5. * Copyright 2011 - 2015 Freescale Semiconductor Inc.
  6. * Copyright 2019-2020 NXP
  7. */
  8. /include/ "p4080.dtsi"
  9. / {
  10. model = "fsl,P4080DS";
  11. compatible = "fsl,P4080DS";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. interrupt-parent = <&mpic>;
  15. aliases {
  16. phy_rgmii = &phyrgmii;
  17. phy5_slot3 = &phy5slot3;
  18. phy6_slot3 = &phy6slot3;
  19. phy7_slot3 = &phy7slot3;
  20. phy8_slot3 = &phy8slot3;
  21. emi1_slot3 = &p4080mdio2;
  22. emi1_slot4 = &p4080mdio1;
  23. emi1_slot5 = &p4080mdio3;
  24. emi1_rgmii = &p4080mdio0;
  25. emi2_slot4 = &p4080xmdio1;
  26. emi2_slot5 = &p4080xmdio3;
  27. };
  28. soc: soc@ffe000000 {
  29. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  30. reg = <0xf 0xfe000000 0 0x00001000>;
  31. fman@400000 {
  32. ethernet@e0000 {
  33. phy-handle = <&phy0>;
  34. phy-connection-type = "sgmii";
  35. };
  36. ethernet@e2000 {
  37. phy-handle = <&phy1>;
  38. phy-connection-type = "sgmii";
  39. };
  40. ethernet@e4000 {
  41. phy-handle = <&phy2>;
  42. phy-connection-type = "sgmii";
  43. };
  44. ethernet@e6000 {
  45. phy-handle = <&phy3>;
  46. phy-connection-type = "sgmii";
  47. };
  48. ethernet@f0000 {
  49. phy-handle = <&phy10>;
  50. phy-connection-type = "xgmii";
  51. };
  52. };
  53. fman@500000 {
  54. ethernet@e0000 {
  55. phy-handle = <&phy5>;
  56. phy-connection-type = "sgmii";
  57. };
  58. ethernet@e2000 {
  59. phy-handle = <&phy6>;
  60. phy-connection-type = "sgmii";
  61. };
  62. ethernet@e4000 {
  63. phy-handle = <&phy7>;
  64. phy-connection-type = "sgmii";
  65. };
  66. ethernet@e6000 {
  67. phy-handle = <&phy8>;
  68. phy-connection-type = "sgmii";
  69. };
  70. ethernet@f0000 {
  71. phy-handle = <&phy11>;
  72. phy-connection-type = "xgmii";
  73. };
  74. };
  75. };
  76. mdio-mux-emi1 {
  77. #address-cells = <1>;
  78. #size-cells = <0>;
  79. compatible = "mdio-mux-gpio", "mdio-mux";
  80. mdio-parent-bus = <&mdio0>;
  81. gpios = <&gpio0 1 0>, <&gpio0 0 0>;
  82. p4080mdio0: mdio@0 {
  83. #address-cells = <1>;
  84. #size-cells = <0>;
  85. reg = <0>;
  86. phyrgmii: ethernet-phy@0 {
  87. reg = <0x0>;
  88. };
  89. };
  90. p4080mdio1: mdio@1 {
  91. #address-cells = <1>;
  92. #size-cells = <0>;
  93. reg = <1>;
  94. phy5: ethernet-phy@1c {
  95. reg = <0x1c>;
  96. };
  97. phy6: ethernet-phy@1d {
  98. reg = <0x1d>;
  99. };
  100. phy7: ethernet-phy@1e {
  101. reg = <0x1e>;
  102. };
  103. phy8: ethernet-phy@1f {
  104. reg = <0x1f>;
  105. };
  106. };
  107. p4080mdio2: mdio@2 {
  108. #address-cells = <1>;
  109. #size-cells = <0>;
  110. reg = <2>;
  111. status = "disabled";
  112. phy5slot3: ethernet-phy@1c {
  113. reg = <0x1c>;
  114. };
  115. phy6slot3: ethernet-phy@1d {
  116. reg = <0x1d>;
  117. };
  118. phy7slot3: ethernet-phy@1e {
  119. reg = <0x1e>;
  120. };
  121. phy8slot3: ethernet-phy@1f {
  122. reg = <0x1f>;
  123. };
  124. };
  125. p4080mdio3: mdio@3 {
  126. #address-cells = <1>;
  127. #size-cells = <0>;
  128. reg = <3>;
  129. phy0: ethernet-phy@1c {
  130. reg = <0x1c>;
  131. };
  132. phy1: ethernet-phy@1d {
  133. reg = <0x1d>;
  134. };
  135. phy2: ethernet-phy@1e {
  136. reg = <0x1e>;
  137. };
  138. phy3: ethernet-phy@1f {
  139. reg = <0x1f>;
  140. };
  141. };
  142. };
  143. mdio-mux-emi2 {
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. compatible = "mdio-mux-gpio", "mdio-mux";
  147. mdio-parent-bus = <&xmdio0>;
  148. gpios = <&gpio0 3 0>, <&gpio0 2 0>;
  149. p4080xmdio1: mdio@1 {
  150. #address-cells = <1>;
  151. #size-cells = <0>;
  152. reg = <1>;
  153. phy11: ethernet-phy@0 {
  154. compatible = "ethernet-phy-ieee802.3-c45";
  155. reg = <0x0>;
  156. };
  157. };
  158. p4080xmdio3: mdio@3 {
  159. #address-cells = <1>;
  160. #size-cells = <0>;
  161. reg = <3>;
  162. phy10: ethernet-phy@4 {
  163. compatible = "ethernet-phy-ieee802.3-c45";
  164. reg = <0x4>;
  165. };
  166. };
  167. };
  168. };
  169. /include/ "p4080si-post.dtsi"