uec_phy.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2005,2010-2011 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Shlomi Gridish
  6. *
  7. * Description: UCC GETH Driver -- PHY handling
  8. * Driver for UEC on QE
  9. * Based on 8260_io/fcc_enet.c
  10. */
  11. #include <common.h>
  12. #include <net.h>
  13. #include <malloc.h>
  14. #include <linux/errno.h>
  15. #include <linux/immap_qe.h>
  16. #include <asm/io.h>
  17. #include "uccf.h"
  18. #include "uec.h"
  19. #include "uec_phy.h"
  20. #include "miiphy.h"
  21. #include <fsl_qe.h>
  22. #include <phy.h>
  23. #define ugphy_printk(format, arg...) \
  24. printf(format "\n", ## arg)
  25. #define ugphy_dbg(format, arg...) \
  26. ugphy_printk(format , ## arg)
  27. #define ugphy_err(format, arg...) \
  28. ugphy_printk(format , ## arg)
  29. #define ugphy_info(format, arg...) \
  30. ugphy_printk(format , ## arg)
  31. #define ugphy_warn(format, arg...) \
  32. ugphy_printk(format , ## arg)
  33. #ifdef UEC_VERBOSE_DEBUG
  34. #define ugphy_vdbg ugphy_dbg
  35. #else
  36. #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
  37. #endif /* UEC_VERBOSE_DEBUG */
  38. /*--------------------------------------------------------------------+
  39. * Fixed PHY (PHY-less) support for Ethernet Ports.
  40. *
  41. * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
  42. *--------------------------------------------------------------------*/
  43. /*
  44. * Some boards do not have a PHY for each ethernet port. These ports are known
  45. * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
  46. * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
  47. * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
  48. * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
  49. * speed and duplex should be for the port.
  50. *
  51. * Example board header configuration file:
  52. * #define CONFIG_FIXED_PHY 0xFFFFFFFF
  53. * #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
  54. *
  55. * #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
  56. * #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
  57. * #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
  58. * #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
  59. *
  60. * #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
  61. * {name, speed, duplex},
  62. *
  63. * #define CONFIG_SYS_FIXED_PHY_PORTS \
  64. * CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \
  65. * CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF)
  66. */
  67. #ifndef CONFIG_FIXED_PHY
  68. #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
  69. #endif
  70. #ifndef CONFIG_SYS_FIXED_PHY_PORTS
  71. #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
  72. #endif
  73. struct fixed_phy_port {
  74. char name[16]; /* ethernet port name */
  75. unsigned int speed; /* specified speed 10,100 or 1000 */
  76. unsigned int duplex; /* specified duplex FULL or HALF */
  77. };
  78. static const struct fixed_phy_port fixed_phy_port[] = {
  79. CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
  80. };
  81. /*--------------------------------------------------------------------+
  82. * BitBang MII support for ethernet ports
  83. *
  84. * Based from MPC8560ADS implementation
  85. *--------------------------------------------------------------------*/
  86. /*
  87. * Example board header file to define bitbang ethernet ports:
  88. *
  89. * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
  90. * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
  91. */
  92. #ifndef CONFIG_SYS_BITBANG_PHY_PORTS
  93. #define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
  94. #endif
  95. #if defined(CONFIG_BITBANGMII)
  96. static const char *bitbang_phy_port[] = {
  97. CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
  98. };
  99. #endif /* CONFIG_BITBANGMII */
  100. static void config_genmii_advert (struct uec_mii_info *mii_info);
  101. static void genmii_setup_forced (struct uec_mii_info *mii_info);
  102. static void genmii_restart_aneg (struct uec_mii_info *mii_info);
  103. static int gbit_config_aneg (struct uec_mii_info *mii_info);
  104. static int genmii_config_aneg (struct uec_mii_info *mii_info);
  105. static int genmii_update_link (struct uec_mii_info *mii_info);
  106. static int genmii_read_status (struct uec_mii_info *mii_info);
  107. u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum);
  108. void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val);
  109. /* Write value to the PHY for this device to the register at regnum, */
  110. /* waiting until the write is done before it returns. All PHY */
  111. /* configuration has to be done through the TSEC1 MIIM regs */
  112. void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
  113. {
  114. uec_private_t *ugeth = (uec_private_t *) dev->priv;
  115. uec_mii_t *ug_regs;
  116. enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
  117. u32 tmp_reg;
  118. #if defined(CONFIG_BITBANGMII)
  119. u32 i = 0;
  120. for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
  121. if (strncmp(dev->name, bitbang_phy_port[i],
  122. sizeof(dev->name)) == 0) {
  123. (void)bb_miiphy_write(NULL, mii_id, regnum, value);
  124. return;
  125. }
  126. }
  127. #endif /* CONFIG_BITBANGMII */
  128. ug_regs = ugeth->uec_mii_regs;
  129. /* Stop the MII management read cycle */
  130. out_be32 (&ug_regs->miimcom, 0);
  131. /* Setting up the MII Mangement Address Register */
  132. tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
  133. out_be32 (&ug_regs->miimadd, tmp_reg);
  134. /* Setting up the MII Mangement Control Register with the value */
  135. out_be32 (&ug_regs->miimcon, (u32) value);
  136. sync();
  137. /* Wait till MII management write is complete */
  138. while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
  139. }
  140. /* Reads from register regnum in the PHY for device dev, */
  141. /* returning the value. Clears miimcom first. All PHY */
  142. /* configuration has to be done through the TSEC1 MIIM regs */
  143. int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
  144. {
  145. uec_private_t *ugeth = (uec_private_t *) dev->priv;
  146. uec_mii_t *ug_regs;
  147. enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
  148. u32 tmp_reg;
  149. u16 value;
  150. #if defined(CONFIG_BITBANGMII)
  151. u32 i = 0;
  152. for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
  153. if (strncmp(dev->name, bitbang_phy_port[i],
  154. sizeof(dev->name)) == 0) {
  155. (void)bb_miiphy_read(NULL, mii_id, regnum, &value);
  156. return (value);
  157. }
  158. }
  159. #endif /* CONFIG_BITBANGMII */
  160. ug_regs = ugeth->uec_mii_regs;
  161. /* Setting up the MII Mangement Address Register */
  162. tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
  163. out_be32 (&ug_regs->miimadd, tmp_reg);
  164. /* clear MII management command cycle */
  165. out_be32 (&ug_regs->miimcom, 0);
  166. sync();
  167. /* Perform an MII management read cycle */
  168. out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
  169. /* Wait till MII management write is complete */
  170. while ((in_be32 (&ug_regs->miimind)) &
  171. (MIIMIND_NOT_VALID | MIIMIND_BUSY));
  172. /* Read MII management status */
  173. value = (u16) in_be32 (&ug_regs->miimstat);
  174. if (value == 0xffff)
  175. ugphy_vdbg
  176. ("read wrong value : mii_id %d,mii_reg %d, base %08x",
  177. mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
  178. return (value);
  179. }
  180. void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
  181. {
  182. if (mii_info->phyinfo->ack_interrupt)
  183. mii_info->phyinfo->ack_interrupt (mii_info);
  184. }
  185. void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
  186. u32 interrupts)
  187. {
  188. mii_info->interrupts = interrupts;
  189. if (mii_info->phyinfo->config_intr)
  190. mii_info->phyinfo->config_intr (mii_info);
  191. }
  192. /* Writes MII_ADVERTISE with the appropriate values, after
  193. * sanitizing advertise to make sure only supported features
  194. * are advertised
  195. */
  196. static void config_genmii_advert (struct uec_mii_info *mii_info)
  197. {
  198. u32 advertise;
  199. u16 adv;
  200. /* Only allow advertising what this PHY supports */
  201. mii_info->advertising &= mii_info->phyinfo->features;
  202. advertise = mii_info->advertising;
  203. /* Setup standard advertisement */
  204. adv = uec_phy_read(mii_info, MII_ADVERTISE);
  205. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
  206. if (advertise & ADVERTISED_10baseT_Half)
  207. adv |= ADVERTISE_10HALF;
  208. if (advertise & ADVERTISED_10baseT_Full)
  209. adv |= ADVERTISE_10FULL;
  210. if (advertise & ADVERTISED_100baseT_Half)
  211. adv |= ADVERTISE_100HALF;
  212. if (advertise & ADVERTISED_100baseT_Full)
  213. adv |= ADVERTISE_100FULL;
  214. uec_phy_write(mii_info, MII_ADVERTISE, adv);
  215. }
  216. static void genmii_setup_forced (struct uec_mii_info *mii_info)
  217. {
  218. u16 ctrl;
  219. u32 features = mii_info->phyinfo->features;
  220. ctrl = uec_phy_read(mii_info, MII_BMCR);
  221. ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
  222. BMCR_SPEED1000 | BMCR_ANENABLE);
  223. ctrl |= BMCR_RESET;
  224. switch (mii_info->speed) {
  225. case SPEED_1000:
  226. if (features & (SUPPORTED_1000baseT_Half
  227. | SUPPORTED_1000baseT_Full)) {
  228. ctrl |= BMCR_SPEED1000;
  229. break;
  230. }
  231. mii_info->speed = SPEED_100;
  232. case SPEED_100:
  233. if (features & (SUPPORTED_100baseT_Half
  234. | SUPPORTED_100baseT_Full)) {
  235. ctrl |= BMCR_SPEED100;
  236. break;
  237. }
  238. mii_info->speed = SPEED_10;
  239. case SPEED_10:
  240. if (features & (SUPPORTED_10baseT_Half
  241. | SUPPORTED_10baseT_Full))
  242. break;
  243. default: /* Unsupported speed! */
  244. ugphy_err ("%s: Bad speed!", mii_info->dev->name);
  245. break;
  246. }
  247. uec_phy_write(mii_info, MII_BMCR, ctrl);
  248. }
  249. /* Enable and Restart Autonegotiation */
  250. static void genmii_restart_aneg (struct uec_mii_info *mii_info)
  251. {
  252. u16 ctl;
  253. ctl = uec_phy_read(mii_info, MII_BMCR);
  254. ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
  255. uec_phy_write(mii_info, MII_BMCR, ctl);
  256. }
  257. static int gbit_config_aneg (struct uec_mii_info *mii_info)
  258. {
  259. u16 adv;
  260. u32 advertise;
  261. if (mii_info->autoneg) {
  262. /* Configure the ADVERTISE register */
  263. config_genmii_advert (mii_info);
  264. advertise = mii_info->advertising;
  265. adv = uec_phy_read(mii_info, MII_CTRL1000);
  266. adv &= ~(ADVERTISE_1000FULL |
  267. ADVERTISE_1000HALF);
  268. if (advertise & SUPPORTED_1000baseT_Half)
  269. adv |= ADVERTISE_1000HALF;
  270. if (advertise & SUPPORTED_1000baseT_Full)
  271. adv |= ADVERTISE_1000FULL;
  272. uec_phy_write(mii_info, MII_CTRL1000, adv);
  273. /* Start/Restart aneg */
  274. genmii_restart_aneg (mii_info);
  275. } else
  276. genmii_setup_forced (mii_info);
  277. return 0;
  278. }
  279. static int marvell_config_aneg (struct uec_mii_info *mii_info)
  280. {
  281. /* The Marvell PHY has an errata which requires
  282. * that certain registers get written in order
  283. * to restart autonegotiation */
  284. uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
  285. uec_phy_write(mii_info, 0x1d, 0x1f);
  286. uec_phy_write(mii_info, 0x1e, 0x200c);
  287. uec_phy_write(mii_info, 0x1d, 0x5);
  288. uec_phy_write(mii_info, 0x1e, 0);
  289. uec_phy_write(mii_info, 0x1e, 0x100);
  290. gbit_config_aneg (mii_info);
  291. return 0;
  292. }
  293. static int genmii_config_aneg (struct uec_mii_info *mii_info)
  294. {
  295. if (mii_info->autoneg) {
  296. /* Speed up the common case, if link is already up, speed and
  297. duplex match, skip auto neg as it already matches */
  298. if (!genmii_read_status(mii_info) && mii_info->link)
  299. if (mii_info->duplex == DUPLEX_FULL &&
  300. mii_info->speed == SPEED_100)
  301. if (mii_info->advertising &
  302. ADVERTISED_100baseT_Full)
  303. return 0;
  304. config_genmii_advert (mii_info);
  305. genmii_restart_aneg (mii_info);
  306. } else
  307. genmii_setup_forced (mii_info);
  308. return 0;
  309. }
  310. static int genmii_update_link (struct uec_mii_info *mii_info)
  311. {
  312. u16 status;
  313. /* Status is read once to clear old link state */
  314. uec_phy_read(mii_info, MII_BMSR);
  315. /*
  316. * Wait if the link is up, and autonegotiation is in progress
  317. * (ie - we're capable and it's not done)
  318. */
  319. status = uec_phy_read(mii_info, MII_BMSR);
  320. if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE)
  321. && !(status & BMSR_ANEGCOMPLETE)) {
  322. int i = 0;
  323. while (!(status & BMSR_ANEGCOMPLETE)) {
  324. /*
  325. * Timeout reached ?
  326. */
  327. if (i > UGETH_AN_TIMEOUT) {
  328. mii_info->link = 0;
  329. return 0;
  330. }
  331. i++;
  332. udelay(1000); /* 1 ms */
  333. status = uec_phy_read(mii_info, MII_BMSR);
  334. }
  335. mii_info->link = 1;
  336. } else {
  337. if (status & BMSR_LSTATUS)
  338. mii_info->link = 1;
  339. else
  340. mii_info->link = 0;
  341. }
  342. return 0;
  343. }
  344. static int genmii_read_status (struct uec_mii_info *mii_info)
  345. {
  346. u16 status;
  347. int err;
  348. /* Update the link, but return if there
  349. * was an error */
  350. err = genmii_update_link (mii_info);
  351. if (err)
  352. return err;
  353. if (mii_info->autoneg) {
  354. status = uec_phy_read(mii_info, MII_STAT1000);
  355. if (status & (LPA_1000FULL | LPA_1000HALF)) {
  356. mii_info->speed = SPEED_1000;
  357. if (status & LPA_1000FULL)
  358. mii_info->duplex = DUPLEX_FULL;
  359. else
  360. mii_info->duplex = DUPLEX_HALF;
  361. } else {
  362. status = uec_phy_read(mii_info, MII_LPA);
  363. if (status & (LPA_10FULL | LPA_100FULL))
  364. mii_info->duplex = DUPLEX_FULL;
  365. else
  366. mii_info->duplex = DUPLEX_HALF;
  367. if (status & (LPA_100FULL | LPA_100HALF))
  368. mii_info->speed = SPEED_100;
  369. else
  370. mii_info->speed = SPEED_10;
  371. }
  372. mii_info->pause = 0;
  373. }
  374. /* On non-aneg, we assume what we put in BMCR is the speed,
  375. * though magic-aneg shouldn't prevent this case from occurring
  376. */
  377. return 0;
  378. }
  379. static int bcm_init(struct uec_mii_info *mii_info)
  380. {
  381. struct eth_device *edev = mii_info->dev;
  382. uec_private_t *uec = edev->priv;
  383. gbit_config_aneg(mii_info);
  384. if ((uec->uec_info->enet_interface_type ==
  385. PHY_INTERFACE_MODE_RGMII_RXID) &&
  386. (uec->uec_info->speed == SPEED_1000)) {
  387. u16 val;
  388. int cnt = 50;
  389. /* Wait for aneg to complete. */
  390. do
  391. val = uec_phy_read(mii_info, MII_BMSR);
  392. while (--cnt && !(val & BMSR_ANEGCOMPLETE));
  393. /* Set RDX clk delay. */
  394. uec_phy_write(mii_info, 0x18, 0x7 | (7 << 12));
  395. val = uec_phy_read(mii_info, 0x18);
  396. /* Set RDX-RXC skew. */
  397. val |= (1 << 8);
  398. val |= (7 | (7 << 12));
  399. /* Write bits 14:0. */
  400. val |= (1 << 15);
  401. uec_phy_write(mii_info, 0x18, val);
  402. }
  403. return 0;
  404. }
  405. static int uec_marvell_init(struct uec_mii_info *mii_info)
  406. {
  407. struct eth_device *edev = mii_info->dev;
  408. uec_private_t *uec = edev->priv;
  409. phy_interface_t iface = uec->uec_info->enet_interface_type;
  410. int speed = uec->uec_info->speed;
  411. if ((speed == SPEED_1000) &&
  412. (iface == PHY_INTERFACE_MODE_RGMII_ID ||
  413. iface == PHY_INTERFACE_MODE_RGMII_RXID ||
  414. iface == PHY_INTERFACE_MODE_RGMII_TXID)) {
  415. int temp;
  416. temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_CR);
  417. if (iface == PHY_INTERFACE_MODE_RGMII_ID) {
  418. temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
  419. } else if (iface == PHY_INTERFACE_MODE_RGMII_RXID) {
  420. temp &= ~MII_M1111_TX_DELAY;
  421. temp |= MII_M1111_RX_DELAY;
  422. } else if (iface == PHY_INTERFACE_MODE_RGMII_TXID) {
  423. temp &= ~MII_M1111_RX_DELAY;
  424. temp |= MII_M1111_TX_DELAY;
  425. }
  426. uec_phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
  427. temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_SR);
  428. temp &= ~MII_M1111_HWCFG_MODE_MASK;
  429. temp |= MII_M1111_HWCFG_MODE_RGMII;
  430. uec_phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
  431. uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
  432. }
  433. return 0;
  434. }
  435. static int marvell_read_status (struct uec_mii_info *mii_info)
  436. {
  437. u16 status;
  438. int err;
  439. /* Update the link, but return if there
  440. * was an error */
  441. err = genmii_update_link (mii_info);
  442. if (err)
  443. return err;
  444. /* If the link is up, read the speed and duplex */
  445. /* If we aren't autonegotiating, assume speeds
  446. * are as set */
  447. if (mii_info->autoneg && mii_info->link) {
  448. int speed;
  449. status = uec_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
  450. /* Get the duplexity */
  451. if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
  452. mii_info->duplex = DUPLEX_FULL;
  453. else
  454. mii_info->duplex = DUPLEX_HALF;
  455. /* Get the speed */
  456. speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
  457. switch (speed) {
  458. case MII_M1011_PHY_SPEC_STATUS_1000:
  459. mii_info->speed = SPEED_1000;
  460. break;
  461. case MII_M1011_PHY_SPEC_STATUS_100:
  462. mii_info->speed = SPEED_100;
  463. break;
  464. default:
  465. mii_info->speed = SPEED_10;
  466. break;
  467. }
  468. mii_info->pause = 0;
  469. }
  470. return 0;
  471. }
  472. static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
  473. {
  474. /* Clear the interrupts by reading the reg */
  475. uec_phy_read(mii_info, MII_M1011_IEVENT);
  476. return 0;
  477. }
  478. static int marvell_config_intr (struct uec_mii_info *mii_info)
  479. {
  480. if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
  481. uec_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
  482. else
  483. uec_phy_write(mii_info, MII_M1011_IMASK,
  484. MII_M1011_IMASK_CLEAR);
  485. return 0;
  486. }
  487. static int dm9161_init (struct uec_mii_info *mii_info)
  488. {
  489. /* Reset the PHY */
  490. uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) |
  491. BMCR_RESET);
  492. /* PHY and MAC connect */
  493. uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) &
  494. ~BMCR_ISOLATE);
  495. uec_phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
  496. config_genmii_advert (mii_info);
  497. /* Start/restart aneg */
  498. genmii_config_aneg (mii_info);
  499. return 0;
  500. }
  501. static int dm9161_config_aneg (struct uec_mii_info *mii_info)
  502. {
  503. return 0;
  504. }
  505. static int dm9161_read_status (struct uec_mii_info *mii_info)
  506. {
  507. u16 status;
  508. int err;
  509. /* Update the link, but return if there was an error */
  510. err = genmii_update_link (mii_info);
  511. if (err)
  512. return err;
  513. /* If the link is up, read the speed and duplex
  514. If we aren't autonegotiating assume speeds are as set */
  515. if (mii_info->autoneg && mii_info->link) {
  516. status = uec_phy_read(mii_info, MII_DM9161_SCSR);
  517. if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
  518. mii_info->speed = SPEED_100;
  519. else
  520. mii_info->speed = SPEED_10;
  521. if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
  522. mii_info->duplex = DUPLEX_FULL;
  523. else
  524. mii_info->duplex = DUPLEX_HALF;
  525. }
  526. return 0;
  527. }
  528. static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
  529. {
  530. /* Clear the interrupt by reading the reg */
  531. uec_phy_read(mii_info, MII_DM9161_INTR);
  532. return 0;
  533. }
  534. static int dm9161_config_intr (struct uec_mii_info *mii_info)
  535. {
  536. if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
  537. uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
  538. else
  539. uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
  540. return 0;
  541. }
  542. static void dm9161_close (struct uec_mii_info *mii_info)
  543. {
  544. }
  545. static int fixed_phy_aneg (struct uec_mii_info *mii_info)
  546. {
  547. mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
  548. return 0;
  549. }
  550. static int fixed_phy_read_status (struct uec_mii_info *mii_info)
  551. {
  552. int i = 0;
  553. for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
  554. if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
  555. strlen(mii_info->dev->name)) == 0) {
  556. mii_info->speed = fixed_phy_port[i].speed;
  557. mii_info->duplex = fixed_phy_port[i].duplex;
  558. mii_info->link = 1; /* Link is always UP */
  559. mii_info->pause = 0;
  560. break;
  561. }
  562. }
  563. return 0;
  564. }
  565. static int smsc_config_aneg (struct uec_mii_info *mii_info)
  566. {
  567. return 0;
  568. }
  569. static int smsc_read_status (struct uec_mii_info *mii_info)
  570. {
  571. u16 status;
  572. int err;
  573. /* Update the link, but return if there
  574. * was an error */
  575. err = genmii_update_link (mii_info);
  576. if (err)
  577. return err;
  578. /* If the link is up, read the speed and duplex */
  579. /* If we aren't autonegotiating, assume speeds
  580. * are as set */
  581. if (mii_info->autoneg && mii_info->link) {
  582. int val;
  583. status = uec_phy_read(mii_info, 0x1f);
  584. val = (status & 0x1c) >> 2;
  585. switch (val) {
  586. case 1:
  587. mii_info->duplex = DUPLEX_HALF;
  588. mii_info->speed = SPEED_10;
  589. break;
  590. case 5:
  591. mii_info->duplex = DUPLEX_FULL;
  592. mii_info->speed = SPEED_10;
  593. break;
  594. case 2:
  595. mii_info->duplex = DUPLEX_HALF;
  596. mii_info->speed = SPEED_100;
  597. break;
  598. case 6:
  599. mii_info->duplex = DUPLEX_FULL;
  600. mii_info->speed = SPEED_100;
  601. break;
  602. }
  603. mii_info->pause = 0;
  604. }
  605. return 0;
  606. }
  607. static struct phy_info phy_info_dm9161 = {
  608. .phy_id = 0x0181b880,
  609. .phy_id_mask = 0x0ffffff0,
  610. .name = "Davicom DM9161E",
  611. .init = dm9161_init,
  612. .config_aneg = dm9161_config_aneg,
  613. .read_status = dm9161_read_status,
  614. .close = dm9161_close,
  615. };
  616. static struct phy_info phy_info_dm9161a = {
  617. .phy_id = 0x0181b8a0,
  618. .phy_id_mask = 0x0ffffff0,
  619. .name = "Davicom DM9161A",
  620. .features = MII_BASIC_FEATURES,
  621. .init = dm9161_init,
  622. .config_aneg = dm9161_config_aneg,
  623. .read_status = dm9161_read_status,
  624. .ack_interrupt = dm9161_ack_interrupt,
  625. .config_intr = dm9161_config_intr,
  626. .close = dm9161_close,
  627. };
  628. static struct phy_info phy_info_marvell = {
  629. .phy_id = 0x01410c00,
  630. .phy_id_mask = 0xffffff00,
  631. .name = "Marvell 88E11x1",
  632. .features = MII_GBIT_FEATURES,
  633. .init = &uec_marvell_init,
  634. .config_aneg = &marvell_config_aneg,
  635. .read_status = &marvell_read_status,
  636. .ack_interrupt = &marvell_ack_interrupt,
  637. .config_intr = &marvell_config_intr,
  638. };
  639. static struct phy_info phy_info_bcm5481 = {
  640. .phy_id = 0x0143bca0,
  641. .phy_id_mask = 0xffffff0,
  642. .name = "Broadcom 5481",
  643. .features = MII_GBIT_FEATURES,
  644. .read_status = genmii_read_status,
  645. .init = bcm_init,
  646. };
  647. static struct phy_info phy_info_fixedphy = {
  648. .phy_id = CONFIG_FIXED_PHY,
  649. .phy_id_mask = CONFIG_FIXED_PHY,
  650. .name = "Fixed PHY",
  651. .config_aneg = fixed_phy_aneg,
  652. .read_status = fixed_phy_read_status,
  653. };
  654. static struct phy_info phy_info_smsclan8700 = {
  655. .phy_id = 0x0007c0c0,
  656. .phy_id_mask = 0xfffffff0,
  657. .name = "SMSC LAN8700",
  658. .features = MII_BASIC_FEATURES,
  659. .config_aneg = smsc_config_aneg,
  660. .read_status = smsc_read_status,
  661. };
  662. static struct phy_info phy_info_genmii = {
  663. .phy_id = 0x00000000,
  664. .phy_id_mask = 0x00000000,
  665. .name = "Generic MII",
  666. .features = MII_BASIC_FEATURES,
  667. .config_aneg = genmii_config_aneg,
  668. .read_status = genmii_read_status,
  669. };
  670. static struct phy_info *phy_info[] = {
  671. &phy_info_dm9161,
  672. &phy_info_dm9161a,
  673. &phy_info_marvell,
  674. &phy_info_bcm5481,
  675. &phy_info_smsclan8700,
  676. &phy_info_fixedphy,
  677. &phy_info_genmii,
  678. NULL
  679. };
  680. u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum)
  681. {
  682. return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
  683. }
  684. void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
  685. {
  686. mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
  687. }
  688. /* Use the PHY ID registers to determine what type of PHY is attached
  689. * to device dev. return a struct phy_info structure describing that PHY
  690. */
  691. struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
  692. {
  693. u16 phy_reg;
  694. u32 phy_ID;
  695. int i;
  696. struct phy_info *theInfo = NULL;
  697. /* Grab the bits from PHYIR1, and put them in the upper half */
  698. phy_reg = uec_phy_read(mii_info, MII_PHYSID1);
  699. phy_ID = (phy_reg & 0xffff) << 16;
  700. /* Grab the bits from PHYIR2, and put them in the lower half */
  701. phy_reg = uec_phy_read(mii_info, MII_PHYSID2);
  702. phy_ID |= (phy_reg & 0xffff);
  703. /* loop through all the known PHY types, and find one that */
  704. /* matches the ID we read from the PHY. */
  705. for (i = 0; phy_info[i]; i++)
  706. if (phy_info[i]->phy_id ==
  707. (phy_ID & phy_info[i]->phy_id_mask)) {
  708. theInfo = phy_info[i];
  709. break;
  710. }
  711. /* This shouldn't happen, as we have generic PHY support */
  712. if (theInfo == NULL) {
  713. ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
  714. return NULL;
  715. } else {
  716. ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
  717. }
  718. return theInfo;
  719. }
  720. void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type,
  721. int speed)
  722. {
  723. uec_private_t *uec = (uec_private_t *) dev->priv;
  724. struct uec_mii_info *mii_info;
  725. u16 status;
  726. if (!uec->mii_info) {
  727. printf ("%s: the PHY not initialized\n", __FUNCTION__);
  728. return;
  729. }
  730. mii_info = uec->mii_info;
  731. if (type == PHY_INTERFACE_MODE_RGMII) {
  732. if (speed == SPEED_100) {
  733. uec_phy_write(mii_info, 0x00, 0x9140);
  734. uec_phy_write(mii_info, 0x1d, 0x001f);
  735. uec_phy_write(mii_info, 0x1e, 0x200c);
  736. uec_phy_write(mii_info, 0x1d, 0x0005);
  737. uec_phy_write(mii_info, 0x1e, 0x0000);
  738. uec_phy_write(mii_info, 0x1e, 0x0100);
  739. uec_phy_write(mii_info, 0x09, 0x0e00);
  740. uec_phy_write(mii_info, 0x04, 0x01e1);
  741. uec_phy_write(mii_info, 0x00, 0x9140);
  742. uec_phy_write(mii_info, 0x00, 0x1000);
  743. mdelay(100);
  744. uec_phy_write(mii_info, 0x00, 0x2900);
  745. uec_phy_write(mii_info, 0x14, 0x0cd2);
  746. uec_phy_write(mii_info, 0x00, 0xa100);
  747. uec_phy_write(mii_info, 0x09, 0x0000);
  748. uec_phy_write(mii_info, 0x1b, 0x800b);
  749. uec_phy_write(mii_info, 0x04, 0x05e1);
  750. uec_phy_write(mii_info, 0x00, 0xa100);
  751. uec_phy_write(mii_info, 0x00, 0x2100);
  752. mdelay(1000);
  753. } else if (speed == SPEED_10) {
  754. uec_phy_write(mii_info, 0x14, 0x8e40);
  755. uec_phy_write(mii_info, 0x1b, 0x800b);
  756. uec_phy_write(mii_info, 0x14, 0x0c82);
  757. uec_phy_write(mii_info, 0x00, 0x8100);
  758. mdelay(1000);
  759. }
  760. }
  761. /* handle 88e1111 rev.B2 erratum 5.6 */
  762. if (mii_info->autoneg) {
  763. status = uec_phy_read(mii_info, MII_BMCR);
  764. uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE);
  765. }
  766. /* now the B2 will correctly report autoneg completion status */
  767. }
  768. void change_phy_interface_mode (struct eth_device *dev,
  769. phy_interface_t type, int speed)
  770. {
  771. #ifdef CONFIG_PHY_MODE_NEED_CHANGE
  772. marvell_phy_interface_mode (dev, type, speed);
  773. #endif
  774. }