smc91111.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*------------------------------------------------------------------------
  3. . smc91111.c
  4. . This is a driver for SMSC's 91C111 single-chip Ethernet device.
  5. .
  6. . (C) Copyright 2002
  7. . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  8. . Rolf Offermanns <rof@sysgo.de>
  9. .
  10. . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
  11. . Developed by Simple Network Magic Corporation (SNMC)
  12. . Copyright (C) 1996 by Erik Stahlman (ES)
  13. .
  14. .
  15. . Information contained in this file was obtained from the LAN91C111
  16. . manual from SMC. To get a copy, if you really want one, you can find
  17. . information under www.smsc.com.
  18. .
  19. .
  20. . "Features" of the SMC chip:
  21. . Integrated PHY/MAC for 10/100BaseT Operation
  22. . Supports internal and external MII
  23. . Integrated 8K packet memory
  24. . EEPROM interface for configuration
  25. .
  26. . Arguments:
  27. . io = for the base address
  28. . irq = for the IRQ
  29. .
  30. . author:
  31. . Erik Stahlman ( erik@vt.edu )
  32. . Daris A Nevil ( dnevil@snmc.com )
  33. .
  34. .
  35. . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
  36. .
  37. . Sources:
  38. . o SMSC LAN91C111 databook (www.smsc.com)
  39. . o smc9194.c by Erik Stahlman
  40. . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
  41. .
  42. . History:
  43. . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
  44. . 10/17/01 Marco Hasewinkel Modify for DNP/1110
  45. . 07/25/01 Woojung Huh Modify for ADS Bitsy
  46. . 04/25/01 Daris A Nevil Initial public release through SMSC
  47. . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
  48. ----------------------------------------------------------------------------*/
  49. #include <common.h>
  50. #include <command.h>
  51. #include <config.h>
  52. #include <malloc.h>
  53. #include "smc91111.h"
  54. #include <net.h>
  55. /* Use power-down feature of the chip */
  56. #define POWER_DOWN 0
  57. #define NO_AUTOPROBE
  58. #define SMC_DEBUG 0
  59. #if SMC_DEBUG > 1
  60. static const char version[] =
  61. "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
  62. #endif
  63. /* Autonegotiation timeout in seconds */
  64. #ifndef CONFIG_SMC_AUTONEG_TIMEOUT
  65. #define CONFIG_SMC_AUTONEG_TIMEOUT 10
  66. #endif
  67. /*------------------------------------------------------------------------
  68. .
  69. . Configuration options, for the experienced user to change.
  70. .
  71. -------------------------------------------------------------------------*/
  72. /*
  73. . Wait time for memory to be free. This probably shouldn't be
  74. . tuned that much, as waiting for this means nothing else happens
  75. . in the system
  76. */
  77. #define MEMORY_WAIT_TIME 16
  78. #if (SMC_DEBUG > 2 )
  79. #define PRINTK3(args...) printf(args)
  80. #else
  81. #define PRINTK3(args...)
  82. #endif
  83. #if SMC_DEBUG > 1
  84. #define PRINTK2(args...) printf(args)
  85. #else
  86. #define PRINTK2(args...)
  87. #endif
  88. #ifdef SMC_DEBUG
  89. #define PRINTK(args...) printf(args)
  90. #else
  91. #define PRINTK(args...)
  92. #endif
  93. /*------------------------------------------------------------------------
  94. .
  95. . The internal workings of the driver. If you are changing anything
  96. . here with the SMC stuff, you should have the datasheet and know
  97. . what you are doing.
  98. .
  99. -------------------------------------------------------------------------*/
  100. /* Memory sizing constant */
  101. #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
  102. #ifndef CONFIG_SMC91111_BASE
  103. #error "SMC91111 Base address must be passed to initialization funciton"
  104. /* #define CONFIG_SMC91111_BASE 0x20000300 */
  105. #endif
  106. #define SMC_DEV_NAME "SMC91111"
  107. #define SMC_PHY_ADDR 0x0000
  108. #define SMC_ALLOC_MAX_TRY 5
  109. #define SMC_TX_TIMEOUT 30
  110. #define SMC_PHY_CLOCK_DELAY 1000
  111. #define ETH_ZLEN 60
  112. #ifdef CONFIG_SMC_USE_32_BIT
  113. #define USE_32_BIT 1
  114. #else
  115. #undef USE_32_BIT
  116. #endif
  117. #ifdef SHARED_RESOURCES
  118. extern void swap_to(int device_id);
  119. #else
  120. # define swap_to(x)
  121. #endif
  122. #ifndef CONFIG_SMC91111_EXT_PHY
  123. static void smc_phy_configure(struct eth_device *dev);
  124. #endif /* !CONFIG_SMC91111_EXT_PHY */
  125. /*
  126. ------------------------------------------------------------
  127. .
  128. . Internal routines
  129. .
  130. ------------------------------------------------------------
  131. */
  132. #ifdef CONFIG_SMC_USE_IOFUNCS
  133. /*
  134. * input and output functions
  135. *
  136. * Implemented due to inx,outx macros accessing the device improperly
  137. * and putting the device into an unkown state.
  138. *
  139. * For instance, on Sharp LPD7A400 SDK, affects were chip memory
  140. * could not be free'd (hence the alloc failures), duplicate packets,
  141. * packets being corrupt (shifted) on the wire, etc. Switching to the
  142. * inx,outx functions fixed this problem.
  143. */
  144. static inline word SMC_inw(struct eth_device *dev, dword offset)
  145. {
  146. word v;
  147. v = *((volatile word*)(dev->iobase + offset));
  148. barrier(); *(volatile u32*)(0xc0000000);
  149. return v;
  150. }
  151. static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
  152. {
  153. *((volatile word*)(dev->iobase + offset)) = value;
  154. barrier(); *(volatile u32*)(0xc0000000);
  155. }
  156. static inline byte SMC_inb(struct eth_device *dev, dword offset)
  157. {
  158. word _w;
  159. _w = SMC_inw(dev, offset & ~((dword)1));
  160. return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
  161. }
  162. static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
  163. {
  164. word _w;
  165. _w = SMC_inw(dev, offset & ~((dword)1));
  166. if (offset & 1)
  167. *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
  168. (value<<8) | (_w & 0x00ff);
  169. else
  170. *((volatile word*)(dev->iobase + offset)) =
  171. value | (_w & 0xff00);
  172. }
  173. static inline void SMC_insw(struct eth_device *dev, dword offset,
  174. volatile uchar* buf, dword len)
  175. {
  176. volatile word *p = (volatile word *)buf;
  177. while (len-- > 0) {
  178. *p++ = SMC_inw(dev, offset);
  179. barrier();
  180. *((volatile u32*)(0xc0000000));
  181. }
  182. }
  183. static inline void SMC_outsw(struct eth_device *dev, dword offset,
  184. uchar* buf, dword len)
  185. {
  186. volatile word *p = (volatile word *)buf;
  187. while (len-- > 0) {
  188. SMC_outw(dev, *p++, offset);
  189. barrier();
  190. *(volatile u32*)(0xc0000000);
  191. }
  192. }
  193. #endif /* CONFIG_SMC_USE_IOFUNCS */
  194. /*
  195. . A rather simple routine to print out a packet for debugging purposes.
  196. */
  197. #if SMC_DEBUG > 2
  198. static void print_packet( byte *, int );
  199. #endif
  200. #define tx_done(dev) 1
  201. static int poll4int (struct eth_device *dev, byte mask, int timeout)
  202. {
  203. int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
  204. int is_timeout = 0;
  205. word old_bank = SMC_inw (dev, BSR_REG);
  206. PRINTK2 ("Polling...\n");
  207. SMC_SELECT_BANK (dev, 2);
  208. while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
  209. if (get_timer (0) >= tmo) {
  210. is_timeout = 1;
  211. break;
  212. }
  213. }
  214. /* restore old bank selection */
  215. SMC_SELECT_BANK (dev, old_bank);
  216. if (is_timeout)
  217. return 1;
  218. else
  219. return 0;
  220. }
  221. /* Only one release command at a time, please */
  222. static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
  223. {
  224. int count = 0;
  225. /* assume bank 2 selected */
  226. while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
  227. udelay(1); /* Wait until not busy */
  228. if (++count > 200)
  229. break;
  230. }
  231. }
  232. /*
  233. . Function: smc_reset( void )
  234. . Purpose:
  235. . This sets the SMC91111 chip to its normal state, hopefully from whatever
  236. . mess that any other DOS driver has put it in.
  237. .
  238. . Maybe I should reset more registers to defaults in here? SOFTRST should
  239. . do that for me.
  240. .
  241. . Method:
  242. . 1. send a SOFT RESET
  243. . 2. wait for it to finish
  244. . 3. enable autorelease mode
  245. . 4. reset the memory management unit
  246. . 5. clear all interrupts
  247. .
  248. */
  249. static void smc_reset (struct eth_device *dev)
  250. {
  251. PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
  252. /* This resets the registers mostly to defaults, but doesn't
  253. affect EEPROM. That seems unnecessary */
  254. SMC_SELECT_BANK (dev, 0);
  255. SMC_outw (dev, RCR_SOFTRST, RCR_REG);
  256. /* Setup the Configuration Register */
  257. /* This is necessary because the CONFIG_REG is not affected */
  258. /* by a soft reset */
  259. SMC_SELECT_BANK (dev, 1);
  260. #if defined(CONFIG_SMC91111_EXT_PHY)
  261. SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
  262. #else
  263. SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
  264. #endif
  265. /* Release from possible power-down state */
  266. /* Configuration register is not affected by Soft Reset */
  267. SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
  268. CONFIG_REG);
  269. SMC_SELECT_BANK (dev, 0);
  270. /* this should pause enough for the chip to be happy */
  271. udelay(10);
  272. /* Disable transmit and receive functionality */
  273. SMC_outw (dev, RCR_CLEAR, RCR_REG);
  274. SMC_outw (dev, TCR_CLEAR, TCR_REG);
  275. /* set the control register */
  276. SMC_SELECT_BANK (dev, 1);
  277. SMC_outw (dev, CTL_DEFAULT, CTL_REG);
  278. /* Reset the MMU */
  279. SMC_SELECT_BANK (dev, 2);
  280. smc_wait_mmu_release_complete (dev);
  281. SMC_outw (dev, MC_RESET, MMU_CMD_REG);
  282. while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
  283. udelay(1); /* Wait until not busy */
  284. /* Note: It doesn't seem that waiting for the MMU busy is needed here,
  285. but this is a place where future chipsets _COULD_ break. Be wary
  286. of issuing another MMU command right after this */
  287. /* Disable all interrupts */
  288. SMC_outb (dev, 0, IM_REG);
  289. }
  290. /*
  291. . Function: smc_enable
  292. . Purpose: let the chip talk to the outside work
  293. . Method:
  294. . 1. Enable the transmitter
  295. . 2. Enable the receiver
  296. . 3. Enable interrupts
  297. */
  298. static void smc_enable(struct eth_device *dev)
  299. {
  300. PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
  301. SMC_SELECT_BANK( dev, 0 );
  302. /* see the header file for options in TCR/RCR DEFAULT*/
  303. SMC_outw( dev, TCR_DEFAULT, TCR_REG );
  304. SMC_outw( dev, RCR_DEFAULT, RCR_REG );
  305. /* clear MII_DIS */
  306. /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
  307. }
  308. /*
  309. . Function: smc_halt
  310. . Purpose: closes down the SMC91xxx chip.
  311. . Method:
  312. . 1. zero the interrupt mask
  313. . 2. clear the enable receive flag
  314. . 3. clear the enable xmit flags
  315. .
  316. . TODO:
  317. . (1) maybe utilize power down mode.
  318. . Why not yet? Because while the chip will go into power down mode,
  319. . the manual says that it will wake up in response to any I/O requests
  320. . in the register space. Empirical results do not show this working.
  321. */
  322. static void smc_halt(struct eth_device *dev)
  323. {
  324. PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
  325. /* no more interrupts for me */
  326. SMC_SELECT_BANK( dev, 2 );
  327. SMC_outb( dev, 0, IM_REG );
  328. /* and tell the card to stay away from that nasty outside world */
  329. SMC_SELECT_BANK( dev, 0 );
  330. SMC_outb( dev, RCR_CLEAR, RCR_REG );
  331. SMC_outb( dev, TCR_CLEAR, TCR_REG );
  332. swap_to(FLASH);
  333. }
  334. /*
  335. . Function: smc_send(struct net_device * )
  336. . Purpose:
  337. . This sends the actual packet to the SMC9xxx chip.
  338. .
  339. . Algorithm:
  340. . First, see if a saved_skb is available.
  341. . ( this should NOT be called if there is no 'saved_skb'
  342. . Now, find the packet number that the chip allocated
  343. . Point the data pointers at it in memory
  344. . Set the length word in the chip's memory
  345. . Dump the packet to chip memory
  346. . Check if a last byte is needed ( odd length packet )
  347. . if so, set the control flag right
  348. . Tell the card to send it
  349. . Enable the transmit interrupt, so I know if it failed
  350. . Free the kernel data if I actually sent it.
  351. */
  352. static int smc_send(struct eth_device *dev, void *packet, int packet_length)
  353. {
  354. byte packet_no;
  355. byte *buf;
  356. int length;
  357. int numPages;
  358. int try = 0;
  359. int time_out;
  360. byte status;
  361. byte saved_pnr;
  362. word saved_ptr;
  363. /* save PTR and PNR registers before manipulation */
  364. SMC_SELECT_BANK (dev, 2);
  365. saved_pnr = SMC_inb( dev, PN_REG );
  366. saved_ptr = SMC_inw( dev, PTR_REG );
  367. PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
  368. length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
  369. /* allocate memory
  370. ** The MMU wants the number of pages to be the number of 256 bytes
  371. ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
  372. **
  373. ** The 91C111 ignores the size bits, but the code is left intact
  374. ** for backwards and future compatibility.
  375. **
  376. ** Pkt size for allocating is data length +6 (for additional status
  377. ** words, length and ctl!)
  378. **
  379. ** If odd size then last byte is included in this header.
  380. */
  381. numPages = ((length & 0xfffe) + 6);
  382. numPages >>= 8; /* Divide by 256 */
  383. if (numPages > 7) {
  384. printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
  385. return 0;
  386. }
  387. /* now, try to allocate the memory */
  388. SMC_SELECT_BANK (dev, 2);
  389. SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
  390. /* FIXME: the ALLOC_INT bit never gets set *
  391. * so the following will always give a *
  392. * memory allocation error. *
  393. * same code works in armboot though *
  394. * -ro
  395. */
  396. again:
  397. try++;
  398. time_out = MEMORY_WAIT_TIME;
  399. do {
  400. status = SMC_inb (dev, SMC91111_INT_REG);
  401. if (status & IM_ALLOC_INT) {
  402. /* acknowledge the interrupt */
  403. SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
  404. break;
  405. }
  406. } while (--time_out);
  407. if (!time_out) {
  408. PRINTK2 ("%s: memory allocation, try %d failed ...\n",
  409. SMC_DEV_NAME, try);
  410. if (try < SMC_ALLOC_MAX_TRY)
  411. goto again;
  412. else
  413. return 0;
  414. }
  415. PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
  416. SMC_DEV_NAME, try);
  417. buf = (byte *) packet;
  418. /* If I get here, I _know_ there is a packet slot waiting for me */
  419. packet_no = SMC_inb (dev, AR_REG);
  420. if (packet_no & AR_FAILED) {
  421. /* or isn't there? BAD CHIP! */
  422. printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
  423. return 0;
  424. }
  425. /* we have a packet address, so tell the card to use it */
  426. SMC_outb (dev, packet_no, PN_REG);
  427. /* do not write new ptr value if Write data fifo not empty */
  428. while ( saved_ptr & PTR_NOTEMPTY )
  429. printf ("Write data fifo not empty!\n");
  430. /* point to the beginning of the packet */
  431. SMC_outw (dev, PTR_AUTOINC, PTR_REG);
  432. PRINTK3 ("%s: Trying to xmit packet of length %x\n",
  433. SMC_DEV_NAME, length);
  434. #if SMC_DEBUG > 2
  435. printf ("Transmitting Packet\n");
  436. print_packet (buf, length);
  437. #endif
  438. /* send the packet length ( +6 for status, length and ctl byte )
  439. and the status word ( set to zeros ) */
  440. #ifdef USE_32_BIT
  441. SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
  442. #else
  443. SMC_outw (dev, 0, SMC91111_DATA_REG);
  444. /* send the packet length ( +6 for status words, length, and ctl */
  445. SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
  446. #endif
  447. /* send the actual data
  448. . I _think_ it's faster to send the longs first, and then
  449. . mop up by sending the last word. It depends heavily
  450. . on alignment, at least on the 486. Maybe it would be
  451. . a good idea to check which is optimal? But that could take
  452. . almost as much time as is saved?
  453. */
  454. #ifdef USE_32_BIT
  455. SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
  456. if (length & 0x2)
  457. SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
  458. SMC91111_DATA_REG);
  459. #else
  460. SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
  461. #endif /* USE_32_BIT */
  462. /* Send the last byte, if there is one. */
  463. if ((length & 1) == 0) {
  464. SMC_outw (dev, 0, SMC91111_DATA_REG);
  465. } else {
  466. SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
  467. }
  468. /* and let the chipset deal with it */
  469. SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
  470. /* poll for TX INT */
  471. /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
  472. /* poll for TX_EMPTY INT - autorelease enabled */
  473. if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
  474. /* sending failed */
  475. PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
  476. /* release packet */
  477. /* no need to release, MMU does that now */
  478. /* wait for MMU getting ready (low) */
  479. while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
  480. udelay(10);
  481. }
  482. PRINTK2 ("MMU ready\n");
  483. return 0;
  484. } else {
  485. /* ack. int */
  486. SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
  487. /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
  488. PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
  489. length);
  490. /* release packet */
  491. /* no need to release, MMU does that now */
  492. /* wait for MMU getting ready (low) */
  493. while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
  494. udelay(10);
  495. }
  496. PRINTK2 ("MMU ready\n");
  497. }
  498. /* restore previously saved registers */
  499. SMC_outb( dev, saved_pnr, PN_REG );
  500. SMC_outw( dev, saved_ptr, PTR_REG );
  501. return length;
  502. }
  503. static int smc_write_hwaddr(struct eth_device *dev)
  504. {
  505. int i;
  506. swap_to(ETHERNET);
  507. SMC_SELECT_BANK (dev, 1);
  508. #ifdef USE_32_BIT
  509. for (i = 0; i < 6; i += 2) {
  510. word address;
  511. address = dev->enetaddr[i + 1] << 8;
  512. address |= dev->enetaddr[i];
  513. SMC_outw(dev, address, (ADDR0_REG + i));
  514. }
  515. #else
  516. for (i = 0; i < 6; i++)
  517. SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
  518. #endif
  519. swap_to(FLASH);
  520. return 0;
  521. }
  522. /*
  523. * Open and Initialize the board
  524. *
  525. * Set up everything, reset the card, etc ..
  526. *
  527. */
  528. static int smc_init(struct eth_device *dev, bd_t *bd)
  529. {
  530. swap_to(ETHERNET);
  531. PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
  532. /* reset the hardware */
  533. smc_reset (dev);
  534. smc_enable (dev);
  535. /* Configure the PHY */
  536. #ifndef CONFIG_SMC91111_EXT_PHY
  537. smc_phy_configure (dev);
  538. #endif
  539. /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
  540. /* SMC_SELECT_BANK(dev, 0); */
  541. /* SMC_outw(dev, 0, RPC_REG); */
  542. printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
  543. return 0;
  544. }
  545. /*-------------------------------------------------------------
  546. .
  547. . smc_rcv - receive a packet from the card
  548. .
  549. . There is ( at least ) a packet waiting to be read from
  550. . chip-memory.
  551. .
  552. . o Read the status
  553. . o If an error, record it
  554. . o otherwise, read in the packet
  555. --------------------------------------------------------------
  556. */
  557. static int smc_rcv(struct eth_device *dev)
  558. {
  559. int packet_number;
  560. word status;
  561. word packet_length;
  562. int is_error = 0;
  563. #ifdef USE_32_BIT
  564. dword stat_len;
  565. #endif
  566. byte saved_pnr;
  567. word saved_ptr;
  568. SMC_SELECT_BANK(dev, 2);
  569. /* save PTR and PTR registers */
  570. saved_pnr = SMC_inb( dev, PN_REG );
  571. saved_ptr = SMC_inw( dev, PTR_REG );
  572. packet_number = SMC_inw( dev, RXFIFO_REG );
  573. if ( packet_number & RXFIFO_REMPTY ) {
  574. return 0;
  575. }
  576. PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
  577. /* start reading from the start of the packet */
  578. SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
  579. /* First two words are status and packet_length */
  580. #ifdef USE_32_BIT
  581. stat_len = SMC_inl(dev, SMC91111_DATA_REG);
  582. status = stat_len & 0xffff;
  583. packet_length = stat_len >> 16;
  584. #else
  585. status = SMC_inw( dev, SMC91111_DATA_REG );
  586. packet_length = SMC_inw( dev, SMC91111_DATA_REG );
  587. #endif
  588. packet_length &= 0x07ff; /* mask off top bits */
  589. PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
  590. if ( !(status & RS_ERRORS ) ){
  591. /* Adjust for having already read the first two words */
  592. packet_length -= 4; /*4; */
  593. /* set odd length for bug in LAN91C111, */
  594. /* which never sets RS_ODDFRAME */
  595. /* TODO ? */
  596. #ifdef USE_32_BIT
  597. PRINTK3(" Reading %d dwords (and %d bytes)\n",
  598. packet_length >> 2, packet_length & 3 );
  599. /* QUESTION: Like in the TX routine, do I want
  600. to send the DWORDs or the bytes first, or some
  601. mixture. A mixture might improve already slow PIO
  602. performance */
  603. SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0],
  604. packet_length >> 2);
  605. /* read the left over bytes */
  606. if (packet_length & 3) {
  607. int i;
  608. byte *tail = (byte *)(net_rx_packets[0] +
  609. (packet_length & ~3));
  610. dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
  611. for (i=0; i<(packet_length & 3); i++)
  612. *tail++ = (byte) (leftover >> (8*i)) & 0xff;
  613. }
  614. #else
  615. PRINTK3(" Reading %d words and %d byte(s)\n",
  616. (packet_length >> 1 ), packet_length & 1 );
  617. SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0],
  618. packet_length >> 1);
  619. #endif /* USE_32_BIT */
  620. #if SMC_DEBUG > 2
  621. printf("Receiving Packet\n");
  622. print_packet(net_rx_packets[0], packet_length);
  623. #endif
  624. } else {
  625. /* error ... */
  626. /* TODO ? */
  627. is_error = 1;
  628. }
  629. while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
  630. udelay(1); /* Wait until not busy */
  631. /* error or good, tell the card to get rid of this packet */
  632. SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
  633. while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
  634. udelay(1); /* Wait until not busy */
  635. /* restore saved registers */
  636. SMC_outb( dev, saved_pnr, PN_REG );
  637. SMC_outw( dev, saved_ptr, PTR_REG );
  638. if (!is_error) {
  639. /* Pass the packet up to the protocol layers. */
  640. net_process_received_packet(net_rx_packets[0], packet_length);
  641. return packet_length;
  642. } else {
  643. return 0;
  644. }
  645. }
  646. #if 0
  647. /*------------------------------------------------------------
  648. . Modify a bit in the LAN91C111 register set
  649. .-------------------------------------------------------------*/
  650. static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
  651. unsigned int bit, int val)
  652. {
  653. word regval;
  654. SMC_SELECT_BANK( dev, bank );
  655. regval = SMC_inw( dev, reg );
  656. if (val)
  657. regval |= bit;
  658. else
  659. regval &= ~bit;
  660. SMC_outw( dev, regval, 0 );
  661. return(regval);
  662. }
  663. /*------------------------------------------------------------
  664. . Retrieve a bit in the LAN91C111 register set
  665. .-------------------------------------------------------------*/
  666. static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
  667. {
  668. SMC_SELECT_BANK( dev, bank );
  669. if ( SMC_inw( dev, reg ) & bit)
  670. return(1);
  671. else
  672. return(0);
  673. }
  674. /*------------------------------------------------------------
  675. . Modify a LAN91C111 register (word access only)
  676. .-------------------------------------------------------------*/
  677. static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
  678. {
  679. SMC_SELECT_BANK( dev, bank );
  680. SMC_outw( dev, val, reg );
  681. }
  682. /*------------------------------------------------------------
  683. . Retrieve a LAN91C111 register (word access only)
  684. .-------------------------------------------------------------*/
  685. static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
  686. {
  687. SMC_SELECT_BANK( dev, bank );
  688. return(SMC_inw( dev, reg ));
  689. }
  690. #endif /* 0 */
  691. /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
  692. #if (SMC_DEBUG > 2 )
  693. /*------------------------------------------------------------
  694. . Debugging function for viewing MII Management serial bitstream
  695. .-------------------------------------------------------------*/
  696. static void smc_dump_mii_stream (byte * bits, int size)
  697. {
  698. int i;
  699. printf ("BIT#:");
  700. for (i = 0; i < size; ++i) {
  701. printf ("%d", i % 10);
  702. }
  703. printf ("\nMDOE:");
  704. for (i = 0; i < size; ++i) {
  705. if (bits[i] & MII_MDOE)
  706. printf ("1");
  707. else
  708. printf ("0");
  709. }
  710. printf ("\nMDO :");
  711. for (i = 0; i < size; ++i) {
  712. if (bits[i] & MII_MDO)
  713. printf ("1");
  714. else
  715. printf ("0");
  716. }
  717. printf ("\nMDI :");
  718. for (i = 0; i < size; ++i) {
  719. if (bits[i] & MII_MDI)
  720. printf ("1");
  721. else
  722. printf ("0");
  723. }
  724. printf ("\n");
  725. }
  726. #endif
  727. /*------------------------------------------------------------
  728. . Reads a register from the MII Management serial interface
  729. .-------------------------------------------------------------*/
  730. #ifndef CONFIG_SMC91111_EXT_PHY
  731. static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
  732. {
  733. int oldBank;
  734. int i;
  735. byte mask;
  736. word mii_reg;
  737. byte bits[64];
  738. int clk_idx = 0;
  739. int input_idx;
  740. word phydata;
  741. byte phyaddr = SMC_PHY_ADDR;
  742. /* 32 consecutive ones on MDO to establish sync */
  743. for (i = 0; i < 32; ++i)
  744. bits[clk_idx++] = MII_MDOE | MII_MDO;
  745. /* Start code <01> */
  746. bits[clk_idx++] = MII_MDOE;
  747. bits[clk_idx++] = MII_MDOE | MII_MDO;
  748. /* Read command <10> */
  749. bits[clk_idx++] = MII_MDOE | MII_MDO;
  750. bits[clk_idx++] = MII_MDOE;
  751. /* Output the PHY address, msb first */
  752. mask = (byte) 0x10;
  753. for (i = 0; i < 5; ++i) {
  754. if (phyaddr & mask)
  755. bits[clk_idx++] = MII_MDOE | MII_MDO;
  756. else
  757. bits[clk_idx++] = MII_MDOE;
  758. /* Shift to next lowest bit */
  759. mask >>= 1;
  760. }
  761. /* Output the phy register number, msb first */
  762. mask = (byte) 0x10;
  763. for (i = 0; i < 5; ++i) {
  764. if (phyreg & mask)
  765. bits[clk_idx++] = MII_MDOE | MII_MDO;
  766. else
  767. bits[clk_idx++] = MII_MDOE;
  768. /* Shift to next lowest bit */
  769. mask >>= 1;
  770. }
  771. /* Tristate and turnaround (2 bit times) */
  772. bits[clk_idx++] = 0;
  773. /*bits[clk_idx++] = 0; */
  774. /* Input starts at this bit time */
  775. input_idx = clk_idx;
  776. /* Will input 16 bits */
  777. for (i = 0; i < 16; ++i)
  778. bits[clk_idx++] = 0;
  779. /* Final clock bit */
  780. bits[clk_idx++] = 0;
  781. /* Save the current bank */
  782. oldBank = SMC_inw (dev, BANK_SELECT);
  783. /* Select bank 3 */
  784. SMC_SELECT_BANK (dev, 3);
  785. /* Get the current MII register value */
  786. mii_reg = SMC_inw (dev, MII_REG);
  787. /* Turn off all MII Interface bits */
  788. mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
  789. /* Clock all 64 cycles */
  790. for (i = 0; i < sizeof bits; ++i) {
  791. /* Clock Low - output data */
  792. SMC_outw (dev, mii_reg | bits[i], MII_REG);
  793. udelay(SMC_PHY_CLOCK_DELAY);
  794. /* Clock Hi - input data */
  795. SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
  796. udelay(SMC_PHY_CLOCK_DELAY);
  797. bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
  798. }
  799. /* Return to idle state */
  800. /* Set clock to low, data to low, and output tristated */
  801. SMC_outw (dev, mii_reg, MII_REG);
  802. udelay(SMC_PHY_CLOCK_DELAY);
  803. /* Restore original bank select */
  804. SMC_SELECT_BANK (dev, oldBank);
  805. /* Recover input data */
  806. phydata = 0;
  807. for (i = 0; i < 16; ++i) {
  808. phydata <<= 1;
  809. if (bits[input_idx++] & MII_MDI)
  810. phydata |= 0x0001;
  811. }
  812. #if (SMC_DEBUG > 2 )
  813. printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
  814. phyaddr, phyreg, phydata);
  815. smc_dump_mii_stream (bits, sizeof bits);
  816. #endif
  817. return (phydata);
  818. }
  819. /*------------------------------------------------------------
  820. . Writes a register to the MII Management serial interface
  821. .-------------------------------------------------------------*/
  822. static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
  823. word phydata)
  824. {
  825. int oldBank;
  826. int i;
  827. word mask;
  828. word mii_reg;
  829. byte bits[65];
  830. int clk_idx = 0;
  831. byte phyaddr = SMC_PHY_ADDR;
  832. /* 32 consecutive ones on MDO to establish sync */
  833. for (i = 0; i < 32; ++i)
  834. bits[clk_idx++] = MII_MDOE | MII_MDO;
  835. /* Start code <01> */
  836. bits[clk_idx++] = MII_MDOE;
  837. bits[clk_idx++] = MII_MDOE | MII_MDO;
  838. /* Write command <01> */
  839. bits[clk_idx++] = MII_MDOE;
  840. bits[clk_idx++] = MII_MDOE | MII_MDO;
  841. /* Output the PHY address, msb first */
  842. mask = (byte) 0x10;
  843. for (i = 0; i < 5; ++i) {
  844. if (phyaddr & mask)
  845. bits[clk_idx++] = MII_MDOE | MII_MDO;
  846. else
  847. bits[clk_idx++] = MII_MDOE;
  848. /* Shift to next lowest bit */
  849. mask >>= 1;
  850. }
  851. /* Output the phy register number, msb first */
  852. mask = (byte) 0x10;
  853. for (i = 0; i < 5; ++i) {
  854. if (phyreg & mask)
  855. bits[clk_idx++] = MII_MDOE | MII_MDO;
  856. else
  857. bits[clk_idx++] = MII_MDOE;
  858. /* Shift to next lowest bit */
  859. mask >>= 1;
  860. }
  861. /* Tristate and turnaround (2 bit times) */
  862. bits[clk_idx++] = 0;
  863. bits[clk_idx++] = 0;
  864. /* Write out 16 bits of data, msb first */
  865. mask = 0x8000;
  866. for (i = 0; i < 16; ++i) {
  867. if (phydata & mask)
  868. bits[clk_idx++] = MII_MDOE | MII_MDO;
  869. else
  870. bits[clk_idx++] = MII_MDOE;
  871. /* Shift to next lowest bit */
  872. mask >>= 1;
  873. }
  874. /* Final clock bit (tristate) */
  875. bits[clk_idx++] = 0;
  876. /* Save the current bank */
  877. oldBank = SMC_inw (dev, BANK_SELECT);
  878. /* Select bank 3 */
  879. SMC_SELECT_BANK (dev, 3);
  880. /* Get the current MII register value */
  881. mii_reg = SMC_inw (dev, MII_REG);
  882. /* Turn off all MII Interface bits */
  883. mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
  884. /* Clock all cycles */
  885. for (i = 0; i < sizeof bits; ++i) {
  886. /* Clock Low - output data */
  887. SMC_outw (dev, mii_reg | bits[i], MII_REG);
  888. udelay(SMC_PHY_CLOCK_DELAY);
  889. /* Clock Hi - input data */
  890. SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
  891. udelay(SMC_PHY_CLOCK_DELAY);
  892. bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
  893. }
  894. /* Return to idle state */
  895. /* Set clock to low, data to low, and output tristated */
  896. SMC_outw (dev, mii_reg, MII_REG);
  897. udelay(SMC_PHY_CLOCK_DELAY);
  898. /* Restore original bank select */
  899. SMC_SELECT_BANK (dev, oldBank);
  900. #if (SMC_DEBUG > 2 )
  901. printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
  902. phyaddr, phyreg, phydata);
  903. smc_dump_mii_stream (bits, sizeof bits);
  904. #endif
  905. }
  906. #endif /* !CONFIG_SMC91111_EXT_PHY */
  907. /*------------------------------------------------------------
  908. . Configures the specified PHY using Autonegotiation. Calls
  909. . smc_phy_fixed() if the user has requested a certain config.
  910. .-------------------------------------------------------------*/
  911. #ifndef CONFIG_SMC91111_EXT_PHY
  912. static void smc_phy_configure (struct eth_device *dev)
  913. {
  914. int timeout;
  915. word my_phy_caps; /* My PHY capabilities */
  916. word my_ad_caps; /* My Advertised capabilities */
  917. word status = 0; /*;my status = 0 */
  918. PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
  919. /* Reset the PHY, setting all other bits to zero */
  920. smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
  921. /* Wait for the reset to complete, or time out */
  922. timeout = 6; /* Wait up to 3 seconds */
  923. while (timeout--) {
  924. if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
  925. & PHY_CNTL_RST)) {
  926. /* reset complete */
  927. break;
  928. }
  929. mdelay(500); /* wait 500 millisecs */
  930. }
  931. if (timeout < 1) {
  932. printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
  933. goto smc_phy_configure_exit;
  934. }
  935. /* Read PHY Register 18, Status Output */
  936. /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
  937. /* Enable PHY Interrupts (for register 18) */
  938. /* Interrupts listed here are disabled */
  939. smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
  940. /* Configure the Receive/Phy Control register */
  941. SMC_SELECT_BANK (dev, 0);
  942. SMC_outw (dev, RPC_DEFAULT, RPC_REG);
  943. /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
  944. my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
  945. my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
  946. if (my_phy_caps & PHY_STAT_CAP_T4)
  947. my_ad_caps |= PHY_AD_T4;
  948. if (my_phy_caps & PHY_STAT_CAP_TXF)
  949. my_ad_caps |= PHY_AD_TX_FDX;
  950. if (my_phy_caps & PHY_STAT_CAP_TXH)
  951. my_ad_caps |= PHY_AD_TX_HDX;
  952. if (my_phy_caps & PHY_STAT_CAP_TF)
  953. my_ad_caps |= PHY_AD_10_FDX;
  954. if (my_phy_caps & PHY_STAT_CAP_TH)
  955. my_ad_caps |= PHY_AD_10_HDX;
  956. /* Update our Auto-Neg Advertisement Register */
  957. smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
  958. /* Read the register back. Without this, it appears that when */
  959. /* auto-negotiation is restarted, sometimes it isn't ready and */
  960. /* the link does not come up. */
  961. smc_read_phy_register(dev, PHY_AD_REG);
  962. PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
  963. PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
  964. /* Restart auto-negotiation process in order to advertise my caps */
  965. smc_write_phy_register (dev, PHY_CNTL_REG,
  966. PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
  967. /* Wait for the auto-negotiation to complete. This may take from */
  968. /* 2 to 3 seconds. */
  969. /* Wait for the reset to complete, or time out */
  970. timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
  971. while (timeout--) {
  972. status = smc_read_phy_register (dev, PHY_STAT_REG);
  973. if (status & PHY_STAT_ANEG_ACK) {
  974. /* auto-negotiate complete */
  975. break;
  976. }
  977. mdelay(500); /* wait 500 millisecs */
  978. /* Restart auto-negotiation if remote fault */
  979. if (status & PHY_STAT_REM_FLT) {
  980. printf ("%s: PHY remote fault detected\n",
  981. SMC_DEV_NAME);
  982. /* Restart auto-negotiation */
  983. printf ("%s: PHY restarting auto-negotiation\n",
  984. SMC_DEV_NAME);
  985. smc_write_phy_register (dev, PHY_CNTL_REG,
  986. PHY_CNTL_ANEG_EN |
  987. PHY_CNTL_ANEG_RST |
  988. PHY_CNTL_SPEED |
  989. PHY_CNTL_DPLX);
  990. }
  991. }
  992. if (timeout < 1) {
  993. printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
  994. }
  995. /* Fail if we detected an auto-negotiate remote fault */
  996. if (status & PHY_STAT_REM_FLT) {
  997. printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
  998. }
  999. /* Re-Configure the Receive/Phy Control register */
  1000. SMC_outw (dev, RPC_DEFAULT, RPC_REG);
  1001. smc_phy_configure_exit: ;
  1002. }
  1003. #endif /* !CONFIG_SMC91111_EXT_PHY */
  1004. #if SMC_DEBUG > 2
  1005. static void print_packet( byte * buf, int length )
  1006. {
  1007. int i;
  1008. int remainder;
  1009. int lines;
  1010. printf("Packet of length %d \n", length );
  1011. #if SMC_DEBUG > 3
  1012. lines = length / 16;
  1013. remainder = length % 16;
  1014. for ( i = 0; i < lines ; i ++ ) {
  1015. int cur;
  1016. for ( cur = 0; cur < 8; cur ++ ) {
  1017. byte a, b;
  1018. a = *(buf ++ );
  1019. b = *(buf ++ );
  1020. printf("%02x%02x ", a, b );
  1021. }
  1022. printf("\n");
  1023. }
  1024. for ( i = 0; i < remainder/2 ; i++ ) {
  1025. byte a, b;
  1026. a = *(buf ++ );
  1027. b = *(buf ++ );
  1028. printf("%02x%02x ", a, b );
  1029. }
  1030. printf("\n");
  1031. #endif
  1032. }
  1033. #endif
  1034. int smc91111_initialize(u8 dev_num, int base_addr)
  1035. {
  1036. struct smc91111_priv *priv;
  1037. struct eth_device *dev;
  1038. int i;
  1039. priv = malloc(sizeof(*priv));
  1040. if (!priv)
  1041. return 0;
  1042. dev = malloc(sizeof(*dev));
  1043. if (!dev) {
  1044. free(priv);
  1045. return 0;
  1046. }
  1047. memset(dev, 0, sizeof(*dev));
  1048. priv->dev_num = dev_num;
  1049. dev->priv = priv;
  1050. dev->iobase = base_addr;
  1051. swap_to(ETHERNET);
  1052. SMC_SELECT_BANK(dev, 1);
  1053. for (i = 0; i < 6; ++i)
  1054. dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
  1055. swap_to(FLASH);
  1056. dev->init = smc_init;
  1057. dev->halt = smc_halt;
  1058. dev->send = smc_send;
  1059. dev->recv = smc_rcv;
  1060. dev->write_hwaddr = smc_write_hwaddr;
  1061. sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
  1062. eth_register(dev);
  1063. return 0;
  1064. }