sbc8641d.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
  4. * Copyright 2007 Embedded Specialties, Inc.
  5. * Joe Hamman joe.hamman@embeddedspecialties.com
  6. *
  7. * Copyright 2004 Freescale Semiconductor.
  8. * Jeff Brown
  9. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  10. *
  11. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  12. */
  13. #include <common.h>
  14. #include <command.h>
  15. #include <init.h>
  16. #include <log.h>
  17. #include <pci.h>
  18. #include <asm/processor.h>
  19. #include <asm/immap_86xx.h>
  20. #include <asm/fsl_pci.h>
  21. #include <fsl_ddr_sdram.h>
  22. #include <asm/fsl_serdes.h>
  23. #include <linux/libfdt.h>
  24. #include <fdt_support.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. long int fixed_sdram (void);
  27. int board_early_init_f (void)
  28. {
  29. return 0;
  30. }
  31. int checkboard (void)
  32. {
  33. puts ("Board: Wind River SBC8641D\n");
  34. return 0;
  35. }
  36. int dram_init(void)
  37. {
  38. long dram_size = 0;
  39. #if defined(CONFIG_SPD_EEPROM)
  40. dram_size = fsl_ddr_sdram();
  41. #else
  42. dram_size = fixed_sdram ();
  43. #endif
  44. debug(" DDR: ");
  45. gd->ram_size = dram_size;
  46. return 0;
  47. }
  48. #if defined(CONFIG_SYS_DRAM_TEST)
  49. int testdram(void)
  50. {
  51. uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  52. uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  53. uint *p;
  54. puts ("SDRAM test phase 1:\n");
  55. for (p = pstart; p < pend; p++)
  56. *p = 0xaaaaaaaa;
  57. for (p = pstart; p < pend; p++) {
  58. if (*p != 0xaaaaaaaa) {
  59. printf ("SDRAM test fails at: %08x\n", (uint) p);
  60. return 1;
  61. }
  62. }
  63. puts ("SDRAM test phase 2:\n");
  64. for (p = pstart; p < pend; p++)
  65. *p = 0x55555555;
  66. for (p = pstart; p < pend; p++) {
  67. if (*p != 0x55555555) {
  68. printf ("SDRAM test fails at: %08x\n", (uint) p);
  69. return 1;
  70. }
  71. }
  72. puts ("SDRAM test passed.\n");
  73. return 0;
  74. }
  75. #endif
  76. #if !defined(CONFIG_SPD_EEPROM)
  77. /*
  78. * Fixed sdram init -- doesn't use serial presence detect.
  79. */
  80. long int fixed_sdram (void)
  81. {
  82. #if !defined(CONFIG_SYS_RAMBOOT)
  83. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  84. volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
  85. ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  86. ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
  87. ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
  88. ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
  89. ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  90. ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
  91. ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
  92. ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
  93. ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  94. ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  95. ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  96. ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  97. ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
  98. ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
  99. ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  100. ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  101. ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
  102. ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  103. ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  104. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  105. asm ("sync;isync");
  106. udelay(500);
  107. ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
  108. asm ("sync; isync");
  109. udelay(500);
  110. ddr = &immap->im_ddr2;
  111. ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
  112. ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
  113. ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
  114. ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
  115. ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
  116. ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
  117. ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
  118. ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
  119. ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
  120. ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
  121. ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
  122. ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
  123. ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
  124. ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
  125. ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
  126. ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
  127. ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
  128. ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
  129. ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
  130. ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
  131. asm ("sync;isync");
  132. udelay(500);
  133. ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
  134. asm ("sync; isync");
  135. udelay(500);
  136. #endif
  137. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  138. }
  139. #endif /* !defined(CONFIG_SPD_EEPROM) */
  140. #if defined(CONFIG_PCI)
  141. /*
  142. * Initialize PCI Devices, report devices found.
  143. */
  144. void pci_init_board(void)
  145. {
  146. fsl_pcie_init_board(0);
  147. }
  148. #endif /* CONFIG_PCI */
  149. #if defined(CONFIG_OF_BOARD_SETUP)
  150. int ft_board_setup(void *blob, bd_t *bd)
  151. {
  152. ft_cpu_setup(blob, bd);
  153. FT_FSL_PCI_SETUP;
  154. return 0;
  155. }
  156. #endif
  157. void sbc8641d_reset_board (void)
  158. {
  159. puts ("Resetting board....\n");
  160. }
  161. /*
  162. * get_board_sys_clk
  163. * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
  164. */
  165. unsigned long get_board_sys_clk (ulong dummy)
  166. {
  167. int i;
  168. ulong val = 0;
  169. i = 5;
  170. i &= 0x07;
  171. switch (i) {
  172. case 0:
  173. val = 33000000;
  174. break;
  175. case 1:
  176. val = 40000000;
  177. break;
  178. case 2:
  179. val = 50000000;
  180. break;
  181. case 3:
  182. val = 66000000;
  183. break;
  184. case 4:
  185. val = 83000000;
  186. break;
  187. case 5:
  188. val = 100000000;
  189. break;
  190. case 6:
  191. val = 134000000;
  192. break;
  193. case 7:
  194. val = 166000000;
  195. break;
  196. }
  197. return val;
  198. }
  199. void board_reset(void)
  200. {
  201. #ifdef CONFIG_SYS_RESET_ADDRESS
  202. ulong addr = CONFIG_SYS_RESET_ADDRESS;
  203. /* flush and disable I/D cache */
  204. __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
  205. __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
  206. __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
  207. __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
  208. __asm__ __volatile__ ("sync");
  209. __asm__ __volatile__ ("mtspr 1008, 4");
  210. __asm__ __volatile__ ("isync");
  211. __asm__ __volatile__ ("sync");
  212. __asm__ __volatile__ ("mtspr 1008, 5");
  213. __asm__ __volatile__ ("isync");
  214. __asm__ __volatile__ ("sync");
  215. /*
  216. * SRR0 has system reset vector, SRR1 has default MSR value
  217. * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
  218. */
  219. __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
  220. __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
  221. __asm__ __volatile__ ("mtspr 27, 4");
  222. __asm__ __volatile__ ("rfi");
  223. #endif
  224. }