cache.c 1.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 SiFive, Inc
  4. *
  5. * Authors:
  6. * Pragnesh Patel <pragnesh.patel@sifive.com>
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <linux/bitops.h>
  11. /* Register offsets */
  12. #define L2_CACHE_CONFIG 0x000
  13. #define L2_CACHE_ENABLE 0x008
  14. #define MASK_NUM_WAYS GENMASK(15, 8)
  15. #define NUM_WAYS_SHIFT 8
  16. DECLARE_GLOBAL_DATA_PTR;
  17. int cache_enable_ways(void)
  18. {
  19. const void *blob = gd->fdt_blob;
  20. int node;
  21. fdt_addr_t base;
  22. u32 config;
  23. u32 ways;
  24. volatile u32 *enable;
  25. node = fdt_node_offset_by_compatible(blob, -1,
  26. "sifive,fu540-c000-ccache");
  27. if (node < 0)
  28. return node;
  29. base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
  30. NULL, false);
  31. if (base == FDT_ADDR_T_NONE)
  32. return FDT_ADDR_T_NONE;
  33. config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
  34. ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
  35. enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
  36. /* memory barrier */
  37. mb();
  38. (*enable) = ways - 1;
  39. /* memory barrier */
  40. mb();
  41. return 0;
  42. }