fsp_init.c 5.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Google LLC
  4. */
  5. #include <common.h>
  6. #include <binman.h>
  7. #include <binman_sym.h>
  8. #include <bootstage.h>
  9. #include <cbfs.h>
  10. #include <dm.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <spi.h>
  14. #include <spl.h>
  15. #include <spi_flash.h>
  16. #include <asm/intel_pinctrl.h>
  17. #include <dm/uclass-internal.h>
  18. #include <asm/fsp2/fsp_internal.h>
  19. int arch_cpu_init_dm(void)
  20. {
  21. struct udevice *dev;
  22. ofnode node;
  23. int ret;
  24. /* Make sure pads are set up early in U-Boot */
  25. if (!ll_boot_init() || spl_phase() != PHASE_BOARD_F)
  26. return 0;
  27. /* Probe all pinctrl devices to set up the pads */
  28. ret = uclass_first_device_err(UCLASS_PINCTRL, &dev);
  29. if (ret)
  30. return log_msg_ret("no fsp pinctrl", ret);
  31. node = ofnode_path("fsp");
  32. if (!ofnode_valid(node))
  33. return log_msg_ret("no fsp params", -EINVAL);
  34. ret = pinctrl_config_pads_for_node(dev, node);
  35. if (ret)
  36. return log_msg_ret("pad config", ret);
  37. return ret;
  38. }
  39. #if !defined(CONFIG_TPL_BUILD)
  40. binman_sym_declare(ulong, intel_fsp_m, image_pos);
  41. binman_sym_declare(ulong, intel_fsp_m, size);
  42. /**
  43. * get_cbfs_fsp() - Obtain the FSP by looking up in CBFS
  44. *
  45. * This looks up an FSP in a CBFS. It is used mostly for testing, when booting
  46. * U-Boot from a hybrid image containing coreboot as the first-stage bootloader.
  47. *
  48. * The typical use for this feature is when building a Chrome OS image which
  49. * includes coreboot in it. By adding U-Boot into the 'COREBOOT' CBFS as well,
  50. * it is possible to make coreboot chain-load U-Boot. Thus the initial stages of
  51. * the SoC init can be done by coreboot and the later stages by U-Boot. This is
  52. * a convenient way to start the porting work. The jump to U-Boot can then be
  53. * moved progressively earlier and earlier, until U-Boot takes over all the init
  54. * and you have a native port.
  55. *
  56. * This function looks up a CBFS at a known location and reads the FSP-M from it
  57. * so that U-Boot can init the memory.
  58. *
  59. * This function is not used in the normal boot but is kept here for future
  60. * development.
  61. *
  62. * @type; Type to look up (only FSP_M supported at present)
  63. * @map_base: Base memory address for mapped SPI
  64. * @entry: Returns an entry containing the position of the FSP image
  65. */
  66. static int get_cbfs_fsp(enum fsp_type_t type, ulong map_base,
  67. struct binman_entry *entry)
  68. {
  69. /*
  70. * Use a hard-coded position of CBFS in the ROM for now. It would be
  71. * possible to read the position using the FMAP in the ROM, but since
  72. * this code is only used for development, it doesn't seem worth it.
  73. * Use the 'cbfstool <image> layout' command to get these values, e.g.:
  74. * 'COREBOOT' (CBFS, size 1814528, offset 2117632).
  75. */
  76. ulong cbfs_base = 0x205000;
  77. struct cbfs_priv *cbfs;
  78. int ret;
  79. ret = cbfs_init_mem(map_base + cbfs_base, &cbfs);
  80. if (ret)
  81. return ret;
  82. if (!ret) {
  83. const struct cbfs_cachenode *node;
  84. node = cbfs_find_file(cbfs, "fspm.bin");
  85. if (!node)
  86. return log_msg_ret("fspm node", -ENOENT);
  87. entry->image_pos = (ulong)node->data;
  88. entry->size = node->data_length;
  89. }
  90. return 0;
  91. }
  92. int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry,
  93. bool use_spi_flash, struct udevice **devp,
  94. struct fsp_header **hdrp, ulong *rom_offsetp)
  95. {
  96. ulong mask = CONFIG_ROM_SIZE - 1;
  97. struct udevice *dev;
  98. ulong rom_offset = 0;
  99. uint map_size;
  100. ulong map_base;
  101. uint offset;
  102. int ret;
  103. /*
  104. * Find the devices but don't probe them, since we don't want to
  105. * auto-config PCI before silicon init runs
  106. */
  107. ret = uclass_find_first_device(UCLASS_NORTHBRIDGE, &dev);
  108. if (ret)
  109. return log_msg_ret("Cannot get northbridge", ret);
  110. if (!use_spi_flash) {
  111. struct udevice *sf;
  112. /* Just use the SPI driver to get the memory map */
  113. ret = uclass_find_first_device(UCLASS_SPI_FLASH, &sf);
  114. if (ret)
  115. return log_msg_ret("Cannot get SPI flash", ret);
  116. ret = dm_spi_get_mmap(sf, &map_base, &map_size, &offset);
  117. if (ret)
  118. return log_msg_ret("Could not get flash mmap", ret);
  119. }
  120. if (spl_phase() >= PHASE_BOARD_F) {
  121. if (type != FSP_S)
  122. return -EPROTONOSUPPORT;
  123. ret = binman_entry_find("intel-fsp-s", entry);
  124. if (ret)
  125. return log_msg_ret("binman entry", ret);
  126. if (!use_spi_flash)
  127. rom_offset = (map_base & mask) - CONFIG_ROM_SIZE;
  128. } else {
  129. ret = -ENOENT;
  130. if (false)
  131. /*
  132. * Support using a hybrid image build by coreboot. See
  133. * the function comments for details
  134. */
  135. ret = get_cbfs_fsp(type, map_base, entry);
  136. if (ret) {
  137. ulong mask = CONFIG_ROM_SIZE - 1;
  138. if (type != FSP_M)
  139. return -EPROTONOSUPPORT;
  140. entry->image_pos = binman_sym(ulong, intel_fsp_m,
  141. image_pos);
  142. entry->size = binman_sym(ulong, intel_fsp_m, size);
  143. if (entry->image_pos != BINMAN_SYM_MISSING) {
  144. ret = 0;
  145. if (use_spi_flash)
  146. entry->image_pos &= mask;
  147. else
  148. entry->image_pos += (map_base & mask);
  149. } else {
  150. ret = -ENOENT;
  151. }
  152. }
  153. }
  154. if (ret)
  155. return log_msg_ret("Cannot find FSP", ret);
  156. entry->image_pos += rom_offset;
  157. /*
  158. * Account for the time taken to read memory-mapped SPI flash since in
  159. * this case we don't use the SPI driver and BOOTSTAGE_ID_ACCUM_SPI.
  160. */
  161. if (!use_spi_flash)
  162. bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
  163. ret = fsp_get_header(entry->image_pos, entry->size, use_spi_flash,
  164. hdrp);
  165. if (!use_spi_flash)
  166. bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
  167. if (ret)
  168. return log_msg_ret("fsp_get_header", ret);
  169. *devp = dev;
  170. if (rom_offsetp)
  171. *rom_offsetp = rom_offset;
  172. return 0;
  173. }
  174. #endif