board.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <env.h>
  8. #include <i2c.h>
  9. #include <init.h>
  10. #include <phy.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/soc.h>
  14. #include <linux/delay.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. /* IO expander I2C device */
  17. #define I2C_IO_EXP_ADDR 0x22
  18. #define I2C_IO_CFG_REG_0 0x6
  19. #define I2C_IO_DATA_OUT_REG_0 0x2
  20. #define I2C_IO_REG_0_SATA_OFF 2
  21. #define I2C_IO_REG_0_USB_H_OFF 1
  22. /* The pin control values are the same for DB and Espressobin */
  23. #define PINCTRL_NB_REG_VALUE 0x000173fa
  24. #define PINCTRL_SB_REG_VALUE 0x00007a23
  25. /* Ethernet switch registers */
  26. /* SMI addresses for multi-chip mode */
  27. #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
  28. #define MVEBU_SW_G2_SMI_ADDR (28)
  29. /* Multi-chip mode */
  30. #define MVEBU_SW_SMI_DATA_REG (1)
  31. #define MVEBU_SW_SMI_CMD_REG (0)
  32. #define SW_SMI_CMD_REG_ADDR_OFF 0
  33. #define SW_SMI_CMD_DEV_ADDR_OFF 5
  34. #define SW_SMI_CMD_SMI_OP_OFF 10
  35. #define SW_SMI_CMD_SMI_MODE_OFF 12
  36. #define SW_SMI_CMD_SMI_BUSY_OFF 15
  37. /* Single-chip mode */
  38. /* Switch Port Registers */
  39. #define MVEBU_SW_LINK_CTRL_REG (1)
  40. #define MVEBU_SW_PORT_CTRL_REG (4)
  41. #define MVEBU_SW_PORT_BASE_VLAN (6)
  42. /* Global 2 Registers */
  43. #define MVEBU_G2_SMI_PHY_CMD_REG (24)
  44. #define MVEBU_G2_SMI_PHY_DATA_REG (25)
  45. /*
  46. * Memory Controller Registers
  47. *
  48. * Assembled based on public information:
  49. * https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336
  50. * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
  51. *
  52. * And checked against the written register values for the various topologies:
  53. * https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h
  54. */
  55. #define A3700_CH0_MC_CTRL2_REG MVEBU_REGISTER(0x002c4)
  56. #define A3700_MC_CTRL2_SDRAM_TYPE_MASK 0xf
  57. #define A3700_MC_CTRL2_SDRAM_TYPE_OFFS 4
  58. #define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
  59. #define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
  60. int board_early_init_f(void)
  61. {
  62. return 0;
  63. }
  64. int board_init(void)
  65. {
  66. /* adress of boot parameters */
  67. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  68. return 0;
  69. }
  70. #ifdef CONFIG_BOARD_LATE_INIT
  71. int board_late_init(void)
  72. {
  73. bool ddr4, emmc;
  74. if (env_get("fdtfile"))
  75. return 0;
  76. if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
  77. return 0;
  78. /* If the memory controller has been configured for DDR4, we're running on v7 */
  79. ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
  80. & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
  81. emmc = of_machine_is_compatible("marvell,armada-3720-espressobin-emmc");
  82. if (ddr4 && emmc)
  83. env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb");
  84. else if (ddr4)
  85. env_set("fdtfile", "marvell/armada-3720-espressobin-v7.dtb");
  86. else if (emmc)
  87. env_set("fdtfile", "marvell/armada-3720-espressobin-emmc.dtb");
  88. else
  89. env_set("fdtfile", "marvell/armada-3720-espressobin.dtb");
  90. return 0;
  91. }
  92. #endif
  93. /* Board specific AHCI / SATA enable code */
  94. int board_ahci_enable(void)
  95. {
  96. struct udevice *dev;
  97. int ret;
  98. u8 buf[8];
  99. /* Only DB requres this configuration */
  100. if (!of_machine_is_compatible("marvell,armada-3720-db"))
  101. return 0;
  102. /* Configure IO exander PCA9555: 7bit address 0x22 */
  103. ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
  104. if (ret) {
  105. printf("Cannot find PCA9555: %d\n", ret);
  106. return 0;
  107. }
  108. ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
  109. if (ret) {
  110. printf("Failed to read IO expander value via I2C\n");
  111. return -EIO;
  112. }
  113. /*
  114. * Enable SATA power via IO expander connected via I2C by setting
  115. * the corresponding bit to output mode to enable power for SATA
  116. */
  117. buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
  118. ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
  119. if (ret) {
  120. printf("Failed to set IO expander via I2C\n");
  121. return -EIO;
  122. }
  123. return 0;
  124. }
  125. /* Board specific xHCI enable code */
  126. int board_xhci_enable(fdt_addr_t base)
  127. {
  128. struct udevice *dev;
  129. int ret;
  130. u8 buf[8];
  131. /* Only DB requres this configuration */
  132. if (!of_machine_is_compatible("marvell,armada-3720-db"))
  133. return 0;
  134. /* Configure IO exander PCA9555: 7bit address 0x22 */
  135. ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
  136. if (ret) {
  137. printf("Cannot find PCA9555: %d\n", ret);
  138. return 0;
  139. }
  140. printf("Enable USB VBUS\n");
  141. /*
  142. * Read configuration (direction) and set VBUS pin as output
  143. * (reset pin = output)
  144. */
  145. ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
  146. if (ret) {
  147. printf("Failed to read IO expander value via I2C\n");
  148. return -EIO;
  149. }
  150. buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
  151. ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
  152. if (ret) {
  153. printf("Failed to set IO expander via I2C\n");
  154. return -EIO;
  155. }
  156. /* Read VBUS output value and disable it */
  157. ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
  158. if (ret) {
  159. printf("Failed to read IO expander value via I2C\n");
  160. return -EIO;
  161. }
  162. buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
  163. ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
  164. if (ret) {
  165. printf("Failed to set IO expander via I2C\n");
  166. return -EIO;
  167. }
  168. /*
  169. * Required delay for configuration to settle - must wait for
  170. * power on port is disabled in case VBUS signal was high,
  171. * required 3 seconds delay to let VBUS signal fully settle down
  172. */
  173. mdelay(3000);
  174. /* Enable VBUS power: Set output value of VBUS pin as enabled */
  175. buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
  176. ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
  177. if (ret) {
  178. printf("Failed to set IO expander via I2C\n");
  179. return -EIO;
  180. }
  181. mdelay(500); /* required delay to let output value settle */
  182. return 0;
  183. }
  184. /* Helper function for accessing switch devices in multi-chip connection mode */
  185. static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
  186. int smi_addr, int reg, u16 value)
  187. {
  188. u16 smi_cmd = 0;
  189. if (bus->write(bus, dev_smi_addr, 0,
  190. MVEBU_SW_SMI_DATA_REG, value) != 0) {
  191. printf("Error writing to the PHY addr=%02x reg=%02x\n",
  192. smi_addr, reg);
  193. return -EFAULT;
  194. }
  195. smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
  196. (1 << SW_SMI_CMD_SMI_MODE_OFF) |
  197. (1 << SW_SMI_CMD_SMI_OP_OFF) |
  198. (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
  199. (reg << SW_SMI_CMD_REG_ADDR_OFF);
  200. if (bus->write(bus, dev_smi_addr, 0,
  201. MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
  202. printf("Error writing to the PHY addr=%02x reg=%02x\n",
  203. smi_addr, reg);
  204. return -EFAULT;
  205. }
  206. return 0;
  207. }
  208. /* Bring-up board-specific network stuff */
  209. int board_network_enable(struct mii_dev *bus)
  210. {
  211. if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
  212. return 0;
  213. /*
  214. * FIXME: remove this code once Topaz driver gets available
  215. * A3720 Community Board Only
  216. * Configure Topaz switch (88E6341)
  217. * Restrict output to ports 1,2,3 only from port 0 (CPU)
  218. * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
  219. */
  220. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
  221. MVEBU_SW_PORT_BASE_VLAN, BIT(0));
  222. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
  223. MVEBU_SW_PORT_BASE_VLAN, BIT(0));
  224. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
  225. MVEBU_SW_PORT_BASE_VLAN, BIT(0));
  226. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
  227. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  228. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
  229. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  230. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
  231. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  232. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
  233. MVEBU_SW_PORT_CTRL_REG, 0x7f);
  234. /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
  235. mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
  236. MVEBU_SW_LINK_CTRL_REG, 0xe002);
  237. /* Power up PHY 1, 2, 3 (through Global 2 registers) */
  238. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  239. MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
  240. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  241. MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
  242. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  243. MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
  244. mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
  245. MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
  246. return 0;
  247. }
  248. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  249. int ft_board_setup(void *blob, struct bd_info *bd)
  250. {
  251. int ret;
  252. int spi_off;
  253. int parts_off;
  254. int part_off;
  255. /* Fill SPI MTD partitions for Linux kernel on Espressobin */
  256. if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
  257. return 0;
  258. spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
  259. if (spi_off < 0)
  260. return 0;
  261. /* Do not touch partitions if they are already defined */
  262. if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
  263. return 0;
  264. parts_off = fdt_add_subnode(blob, spi_off, "partitions");
  265. if (parts_off < 0) {
  266. printf("Can't add partitions node: %s\n", fdt_strerror(parts_off));
  267. return 0;
  268. }
  269. ret = fdt_setprop_string(blob, parts_off, "compatible", "fixed-partitions");
  270. if (ret < 0) {
  271. printf("Can't set compatible property: %s\n", fdt_strerror(ret));
  272. return 0;
  273. }
  274. ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
  275. if (ret < 0) {
  276. printf("Can't set #address-cells property: %s\n", fdt_strerror(ret));
  277. return 0;
  278. }
  279. ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
  280. if (ret < 0) {
  281. printf("Can't set #size-cells property: %s\n", fdt_strerror(ret));
  282. return 0;
  283. }
  284. /* Add u-boot-env partition */
  285. part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-env");
  286. if (part_off < 0) {
  287. printf("Can't add partition@u-boot-env node: %s\n", fdt_strerror(part_off));
  288. return 0;
  289. }
  290. ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
  291. if (ret < 0) {
  292. printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
  293. return 0;
  294. }
  295. ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_SIZE);
  296. if (ret < 0) {
  297. printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
  298. return 0;
  299. }
  300. ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
  301. if (ret < 0) {
  302. printf("Can't set partition@u-boot-env label property: %s\n", fdt_strerror(ret));
  303. return 0;
  304. }
  305. /* Add firmware partition */
  306. part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
  307. if (part_off < 0) {
  308. printf("Can't add partition@firmware node: %s\n", fdt_strerror(part_off));
  309. return 0;
  310. }
  311. ret = fdt_setprop_u32(blob, part_off, "reg", 0);
  312. if (ret < 0) {
  313. printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
  314. return 0;
  315. }
  316. ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
  317. if (ret < 0) {
  318. printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
  319. return 0;
  320. }
  321. ret = fdt_setprop_string(blob, part_off, "label", "firmware");
  322. if (ret < 0) {
  323. printf("Can't set partition@firmware label property: %s\n", fdt_strerror(ret));
  324. return 0;
  325. }
  326. return 0;
  327. }
  328. #endif